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g smsun ks57c2408a/2416a 4-bit cmos microcontroller product specification 7? overview the ks57c2408a/2416a single-chip cmos microcontroller is designed for very high performance using samsung's newest 4-bit product development approach, sam4 (samsung arrangeable microcontrollers). its main features are an up-to-12-digit lcd direct drive capability, 8-bit 6-channel a/d converter, and versatile 8-bit and 16-bit counter/ timers. the "2408a/2416a" gives you an excellent design solution for a variety of lcd-related applications. up to 50 pins of the available 80-pin qfp packages can be dedicated to i/o. and eight vectored interrupts provide fast response to internal and external events. in addition, the 2408a/2416a's advanced cmos technology ensures low power consumption and a wide operating voltage range. features memory 512 4-bit ram 8192 8-bit (ks57c2408a) 16384 8-bit (KS57C2416A) data memory mapped i/o oscillation sources crystal, ceramic, rc (main) crystal for subsystem clock main system clock frequency: 4.19 mhz (typical) subsystem clock frequency: 32.768 khz cpu clock divider (4, 8, 64) two power-down modes idle (only cpu clock stops) stop (system clock stops) interrupts 5 internal vectored interrupts 3 external vectored interrupts 2 quasi-interrupts 50 i/o pins 10 input pins 12 output pins 20 configurable i/o pins 8 n-channel open-drain pins 8-bit basic timer 4 interval timer functions 8-bit timer/counter programmable 8-bit timer external event counter arbitrary clock output external clock signal divider serial i/o clock generator 16-bit timer/counter programmable 16-bit timer external event counter arbitrary clock output external clock signal divider watch timer real-time and interval time measurement clock generation for lcd four frequency outputs for buzzer sound lcd controller/driver maximum 12-digit lcd direct drive capability display modes: static, 1/2duty (1/2 bias) 1/3 duty (1/2 or1/3 bias), 1/4duty (1/3 bias) a/d converter six analog input channels 19.09- m s conversion speed at 4.19 mhz 8-bit conversion resolution 8-bit serial i/o interface 8-bit transmit/receive mode 8-bit receive mode lsb-first or msb-first transmission selectable internal/external clock source instruction execution times 0.95, 1.91, 15.3 m s at 4.19 mhz (main) 122 m s at 32.768 khz (subsystem) operating temperature range 40 c to 85 c operating voltage range 2.7 v to 6.0 v package type 80-pin qfp package
ks57c2408a/2416a microcontroller product specification september 1996 7? g electronics smsun g smsun p10.0?10.1 / ad4?d5 p6.0?6.3 / ks0?s3 p3.0 / tclo0 basic timer p0.3 / btco a/d converter arithmetic and logic unit interrupt control block 4-bit accumu- lator stack pointer program counter program status word i/o port 0 lcd driver p8.0?8.11 / seg12?eg23 vlc0?lc2 com0?om3 seg0?eg11 bias input port 1 i/o port 2 i/o port 3 p0.0 / sck p0.1 / so p0.2 / si p0.3 / btco p1.0 / int0 p1.1 / int1 p1.2 / int2 p1.3 / int4 p2.0 / tcl0 p2.1 / tcl1 p2.2 p2.3 p3.0 / tclo0 p3.1 / tclo1 p3.2 / clo avref 512 x 4-bit data memory and stack serial i/o port p0.2 / si p0.1 / so p0.0 / sck p3.3 / buz watch timer 8 k /16 k byte program memory 8-bit timer/ counter 0 p2.0 / tcl0 p2.1 / tcl1 p3.1 / tclo1 16-bit timer/ counter 1 flags decoder logic osc reset xin xtin xout xtout internal interrupts int0, int1, int2, int4 instruction register i/o port 4 i/o port 5 p4.0?4.3 p5.0?5.3 i/o port 6 i/o port 7 p7.0?7.3 / ks4?s7 p9.0?9.3 / ad0?d3 input port 9 input port 10 avss figure 1. ks57c2408a/2416a block diagram
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7? september 1996 seg5 seg4 seg3 seg2 seg1 seg0 av ref av ss p10.1 / ad5 p10.0 / ad4 p9.3 / ad3 p9.2 / ad2 p9.1 / ad1 p9.0 / ad0 xtout xtin xin xout v dd test reset p4.3 p4.2 p4.1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 77 78 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 28 27 26 25 ks57c2408a/2416a (top view) p8.10 / seg22 p8.11 / seg23 com0 com1 com2 com3 bias v lc0 v lc1 v lc2 v ss p0.0 / sck p0.1 / so p0.2 / si p0.3 / btco p1.0 / int0 p1.1 / int1 p1.2 / int2 p1.3 / int4 p2.0 / tcl0 p2.1 / tcl1 p2.2 p2.3 p3.0 / tclo0 seg6 seg7 seg8 p7.0 / ks4 p6.3 / ks3 p8.5 / seg17 p8.6 / seg18 p8.7 / seg19 p8.8 / seg20 p8.9 / seg21 p5.0 p7.3 / ks7 p7.2 / ks6 p7.1 / ks5 p8.0 / seg12 p8.1 / seg13 p8.2 / seg14 p8.3 / seg15 p8.4 / seg16 seg9 seg10 seg11 p3.3 / buz p3.2 / clo p3.1 / tclo1 p6.2 / ks2 p6.1 / ks1 p6.0 / ks0 p4.0 p5.3 p5.2 p5.1 40 39 38 37 36 35 34 33 32 31 30 29 65 66 67 68 69 70 71 72 73 74 75 76 figure 2. ks57c2408a/2416a pin assignments (80?fp)
ks57c2408a/2416a microcontroller product specification september 1996 7? g electronics smsun g smsun table 1. ks57c2408a/2416a pin descriptions pin names pin type description number (80-qfp) share pin p0.0 p0.1 p0.2 p0.3 i/o 4-bit i/o port. 1-bit and 4-bit read/write and test is possible. individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable. 12 13 14 15 sck so si btco p1.0 p1.1 p1.2 p1.3 i 4-bit input port. 1-bit and 4-bit read and test is possible. 3-bit pull-up resistors are software assignable to pins p1.0, p1.1, and p1.2. 16 17 18 19 int0 int1 int2 int4 p2.0 p2.1 p2.2 p2.3 i/o same as port 0. 20 21 22 23 tcl0 tcl1 p3.0 p3.1 p3.2 p3.3 same as port 0. 24 25 26 27 tclo0 tclo1 clo buz p4.0?4.3 p5.0?5.3 4-bit i/o ports. n-channel open-drain output up to 9volts. 1 -, 4-, and 8-bit read/write and test is possible. ports 4 and 5 can be paired to support 8-bit data transfer. pull-up resistors are assignable to individual pins by mask option. 40?3 36?9 p6.0?6.3 p7.0?7.3 4-bit i/o ports. port 6 pins are individually software configurable as input or output. 1-bit and 4-bit read/write and test is possible. 4-bit pull-up resistors are software assignable. ports 6 and 7 can be paired to enable 8-bit data transfer. 28?1 32?5 ks0?s3 ks4?s7 p8.0?8.11 o output port for 1-bit data (for use as cmos driver only). 71?0, 1? seg12 seg23 p9.0?9.3 p10.0?10.1 i input ports for 1-bit or 4-bit data. 1-bit and 4-bit read and test is possible. 51?6 ad0?d3 ad4?d5 clo i/o cpu clock output 26 p3.2 buz 2, 4, 8, or 16 khz frequency output for buzzer sound with 4.19 mhz main system clock or 32.768 khz subsystem clock. 27 p3.3 x in , x out crystal, ceramic, or rc oscillator signal for main system clock. (for external clock input, use x in and input x in 's reverse phase to x out .) 48, 47 xt in , xt out crystal oscillator signal for subsystem clock. (for external clock input, use xt in and input xt in 's reverse phase to xt out ). 49, 50 int0, int1 i external interrupts. the triggering edge for int0 and int1 is selectable. only int0 is synchronized with the system clock. 16?7 p1.0, p1.1
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7? september 1996 table 1. ks57c2408a/2416a pin descriptions (continued) pin names pin type description number (80-qfp) share pin int2 i quasi-interrupt with detection of rising edges 18 p1.2 int4 external interrupt with detection of rising or falling edges 19 p1.3 ks0?s7 i/o quasi-interrupt input with falling edge detection 28?5 p6.0?7.3 tcl0 external clock input for timer/counter 0 20 p2.0 tcl1 external clock input for timer/counter 1 21 p2.1 tclo0 timer/counter 0 clock output 24 p3.0 tclo1 timer/counter 1 clock output 25 p3.1 com0?om3 o lcd common signal output 3? seg0?eg11 lcd segment output 59?0 seg12 seg23 1-bit lcd segment data output 71?0, 1? p8.0?8.11 bias lcd power control 7 v lc0 ? lc2 lcd power supply. voltage dividing resistors are assignable by mask option. 8?0 ad0?d5 i a/d converter analog input channels 51?6 p9.0?9.3 p10.0?10.1 av ss a/d converter ground 57 av ref a/d converter analog reference voltage 58 sck i/o serial i/o interface clock signal 12 p0.0 so serial data output 13 p0.1 si serial data input 14 p0.2 btco basic interval timer clock output 15 p0.3 reset i reset signal 44 v dd main power supply 46 v ss ground 11 test test signal input (must be connected to v ss) 45 note: pull-up resistors for ports 0, 2, 3, 6, and 7 are automatically disabled if they are configured to output mode.
ks57c2408a/2416a microcontroller product specification september 1996 7? g electronics smsun g smsun table 2. supplemental ks57c2408a/2416a pin data pin numbers (80-qfp) pin names share pins i/o type reset value circuit type 1, 2 p8.10, p8.11 seg22?eg23 o low 9 3? com0?om3 o low 8 7 bias 8?0 v lc0 ? lc2 11 v ss 12?5 p0.0?0.3 sck , so, si, btco i/o 6 16?8 p1.0?1.2 int0, int1, int2 i 3 19 p1.3 int4 i 2 20, 21 p2.0, p2.1 tcl0, tcl1 input 6 22, 23 p2.2, p2.3 6 24?7 p3.0?3.3 tclo0, tclo1, clo, buz i/o 5 28?1 p6.0?6.3 ks0?s3 6 32?5 p7.0?7.3 ks4?s7 6 36?9 p5.0?5.3 i/o (note) 10 40?3 p4.0?4.3 i/o (note) 10 44 reset 12 45 test 46 v dd 47, 48 x in , x out 49, 50 xt in , xt out 51?4 p9.0?9.3 ad0?d3 i input 11 55, 56 p10.0, p10.1 ad4, ad5 i input 11 57, 58 av ss , av ref 59?0 seg0?eg11 o low 7 71?0 p8.0?8.9 seg12?eg21 o low 9 note : high level (when pull-up resistors are provided) or high impedance.
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7? september 1996 p - channel in n - channel v dd figure 3. pin circuit type 1 schmitt trigger in figure 4. pin circuit type 2 in p - channel resistor enable v dd pull-up resistor schmitt trigger figure 5. pin circuit type 3 p - channel data output disable out n - channel v dd figure 6. pin circuit type 4 p - channel pull-up resistor resistor enable circuit type 4 data output disable circuit type 1 i/o v dd figure 7. pin circuit type 5 p - channel pull-up resistor resistor enable circuit type 4 data output disable circuit type 2 i/o v dd figure 8. pin circuit type 6 p-ch n-ch p-channel n-channel v lc0 v lc1 lcd segment data v lc2 out figure 9. pin circuit type 7
ks57c2408a/2416a microcontroller product specification september 1996 7? g electronics smsun g smsun p-channel n-channel v lc0 v lc1 v lc2 lcd common data out figure 10. pin circuit type 8 p-ch n-ch p-channel n-channel v lc0 v lc1 v lc2 v dd out lcd segment & port 8 data figure 11. pin circuit type 9 data output disable v dd i/o pull-up resistor (mask option) 9-volt maximum input voltage figure 12. pin circuit type 10 a/d converter internal logic figure 13. pin circuit type 11 in schmitt trigger input v dd figure 14. pin circuit type 12
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7? september 1996 program memory (rom) rom maps for ks57 devices are mask programmable at the factory. in its standard configuration, the device's 8192 8-bit / 16384 8-bit program memory has four areas that are directly addressable by the program counter (pc): 16-byte general-purpose area 8064 / 16256-bytegeneral-purpose area 16-byte area for vector addresses 96-byte instruction reference area general-purpose area (16 bytes) general-purpose area (8064 / 16256 bytes) vector address area (16 bytes) instruction reference area (96 bytes) 0000h 000fh 0010h 001fh 0020h 007fh 0080h 1fffh / 3fffh figure 15. rom map 000ah 000ch 000eh 000fh 76543210 reset intb/int4 int0 int1 ints intt0 intt1 intad 0000h 0002h 0004h 0006h 0008h figure 16. vector address map data memory (ram) in its standard configuration, the 512 4 -bit data memory has five areas: ?2 4-bit working register area 224 4 -bit general-purpose area (also used as stack area) 232 4 -bit general-purpose area ?4 4-bit area for lcd data 128 4-bit area for memory-mapped i/o addresses i/o map for hardware registers table 3 contains detailed information about i/o mapping for peripheral hardware in bank 15 (register locations f80h?ffh).
ks57c2408a/2416a microcontroller product specification september 1996 7?0 g electronics smsun g smsun 1. 'x' means don't care. 2. blank columns indicate ram areas that are not addressable, given the addressing method and enable memory bank (emb) flag setting shown in the column headers. da da.b @hl @h + da.b @wx @wl mema.b memb.@l emb = 0 emb = 1 emb = 0 emb = 1 x x x 000h working registers bank 0 (general registers and stack) 01fh 020h 07fh 080h 0ffh 100h 1e7h 1e8h 1ffh f80h fffh bank 1 (general registers) bank 1 (display registers) bank 15 (peripheral hardware registers) fb0h fbfh ff0h fc0h smb = 0 smb = 1 smb = 15 smb = 1 smb = 0 smb = 1 smb = 15 smb = 1 ram areas addressing mode notes : figure 17. data memory (ram) address structure
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7?1 september 1996 table 3. i/o map for memory bank 15 memory bank 15 addressing mode address register name r/w 1-bit 4-bit 8-bit f81h?80h sp stack pointer r/w no no yes f85h bmod basic timer mode register w .3 yes no f87h?86h bcnt basic timer counter register r no no yes f89h?88h wmod watch timer mode register w .3 (r) no yes f8dh?8ch lmod lcd mode register w .3 (w) no yes f8eh lcon lcd control register w no yes no f91h?90h tmod0 timer/counter 0 mode register w .3 (w) no yes f92h toe1 toe0 boe "0" r/w yes yes no f95h?94h tcnt0 timer/counter 0 counter register r no no yes f97h?96h tref0 timer/counter 0 reference reg w no no yes fa1h?a0h tmod1 timer/counter 1 mode register w .3 (w) no yes fa5h?a4h tcnt1 a timer/counter 1 counter register a r no no yes fa7h?a6h tcnt1 b timer/counter 1 counter register b r no no yes fa9h?a8h tref1 a timer/counter 1 reference reg a w no no yes fabh?aah tref1 b timer/counter 1 reference reg b w no no yes fb0h psw is1 is0 emb erb r/w yes yes yes fb1h c (1) sc2 sc1 sc0 r no no fb2h ipr interrupt priority register w ime yes no fb3h pcon power control register w no yes no fb4h imod0 external interrupt 0 mode register w no yes no fb5h imod1 external interrupt 1 mode register fb6h imod2 external interrupt 2 mode register fb7h scmod system clock mode register w yes no no fb8h ie4 irq4 ieb irqb r/w yes yes no fbah "0" "0" iew irqw fbbh iead irqad iet1 irqt1 fbch "0" "0" iet0 irqt0 fbdh "0" "0" ies irqs fbeh ie1 irq1 ie0 irq0 fbfh "0" "0" ie2 irq2 fc0h bsc0 bit sequential carrier 0 r/w yes yes yes fc1h bsc1 bit sequential carrier 1 fc2h bsc2 bit sequential carrier 2 yes
ks57c2408a/2416a microcontroller product specification september 1996 7?2 g electronics smsun g smsun table 3. i/o map for memory bank 15 (continued) memory bank 15 addressing mode address register name r/w 1-bit 4-bit 8-bit fc3h bsc3 bit sequential carrier 3 r/w yes yes yes fd0h clmod clock mode register w no yes no fd9h?d8h adata adc data register r no no yes fdah admod adc mode register r/w yes yes no fdbh aflag adc flag register (2) yes yes no fddh?dch pumod pull-up mode register w no no yes fe1h?e0h smod sio mode register w .3 no yes fe5h?e4h sbuf sio buffer register r/w no no yes fe9h?e8h pmg1 port mode group 1 w no no yes febh?eah pmg2 port mode group 2 fedh?ech pmg3 port mode group 3 ff0h p0 port 0 r/w yes yes no ff1h p1 port 1 r yes yes no ff2h p2 port 2 r/w yes yes no ff3h p3 port 3 r/w yes yes no ff4h p4 port 4 r/w yes yes yes ff5h p5 port 5 r/w yes yes ff6h p6 port 6 r/w yes yes yes ff7h p7 port 7 r/w yes yes ff8h p9 port 9 r yes yes no ff9h p10 port 10 r yes yes notes:5 1. the carry flag can be read or written by specific bit manipulation instructions only. 2. the adstr bit of the aflag register is 1- bit or 4-bit write-only; the eoc bit is 1-bit or 4-bit read-only.
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7?3 september 1996 bit sequential carrier (bsc) the bit sequential carrier (bsc) is a 16-bit general register that is mapped in data memory bank 15. using the bsc, you can specify sequential addresses and bit locations using 1-bit indirect addressing (memb.@l). bsc bit addressing is independent of the current emb value. in this way, programs can process 16-bit data by moving the bit location sequentially and then incrementing or decrementing the value of the l register. for 8-bit manipulations, the 4-bit register names bsc0 and bsc2 must be specified and the upper and lower 8 bits manipulated separately. if the values of the l register are 0h at bsc0.@l, the address and bit location assignment is fc0h.0. if the l register content is fh at bsc0.@l, the address and bit location assignment is fc3h.3. table 4. bsc register organization name address bit 3 bit 2 bit 1 bit 0 bsc0 fc0h bsc0.3 bsc0.2 bsc0.1 bsc0.0 bsc1 fc1h bsc1.3 bsc1.2 bsc1.1 bsc1.0 bsc2 fc2h bsc2.3 bsc2.2 bsc2.1 bsc2.0 bsc3 fc3h bsc3.3 bsc3.2 bsc3.1 bsc3.0 + programming tip ?using the bsc register to output 16-bit data to use the bit sequential carrier (bsc) register to output 16-bit data (5937h) to the p3.0 pin: bits emb smb 15 ld ea,#37h ; ld bsc0,ea ; bsc0 ? a, bsc1 ? e ld ea,#59h ; ld bsc2,ea ; bsc2 ? a, bsc3 ? e smb 0 ld l,#0h ; agn ldb c,bsc0.@l ; ldb p3.0,c ; p3.0 ? c incs l jr agn ret
ks57c2408a/2416a microcontroller product specification september 1996 7?4 g electronics smsun g smsun interrupts the ks57c2408a/2416a has three external interrupts, five internal interrupts and two quasi-interrupts. table 5 shows the conditions for interrupt generation. the request flags that allow these interrupts to be generated are cleared by hardware when the service routine is vectored. the quasi-interrupt's request flags must be cleared by software. irqb irq4 irq0 irq1 irqs irqt0 irqt1 irqad irqw irq2 iead iet1 iet0 ies ie1 ie0 ie4 ieb imod1 imod0 intb ints intt0 intt1 intad intw # @ @ power-down mode release signal ime ipr is1 is0 interrupt control unit vector interrupt generator # = noise filtering circuit @ = edge detection circuit selector imod2 int2 ks0?s7 iew ie2 int1 int0 int4 figure 18. interrupt control circuit diagram
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7?5 september 1996 table 5. interrupt request flag conditions and priorities interrupt source internal / external condition for irqx flag setting interrupt priority request flag name intb i reference time interval signal from basic timer 1 irqb int4 e both rising and falling edges detected at int4 1 irq4 int0 e rising or falling edge detected at int0 pin 2 irq0 int1 e rising or falling edge detected at int1 pin 3 irq1 ints i completion signal for serial transmit-and- receive or receive-only operation 4 irqs intt0 i signals for tcnt0 and tref0 registers match 5 irqt0 intt1 i signals for tcnt1 and tref1 registers match 6 irqt1 intad i analog-to-digital conversion is completed 7 irqad int2 * e rising edge detected at int2 or else a falling edge is detected at any of the ks0?s7 pins irq2 intw i time interval of 0.5 s or 3.19 ms irqw * the quasi-interrupt int2 is only used for testing incoming signals. interrupt enable flags iex flags, when set to "1", enable specific interrupt requests to be serviced. when the interrupt request flag is set to "1", an interrupt will not be serviced until its corresponding iex flag is also enabled. the ipr register contains a global disable bit, ime, which disables all interrupt at once. table 6. interrupt enable and request flags address bit 3 bit 2 bit 1 bit 0 fb8h ie4 irq4 ieb irqb fbah 0 0 iew irqw fbbh iead irqad iet1 irqt1 fbch 0 0 iet0 irqt0 fbdh 0 0 ies irqs fbeh ie1 irq1 ie0 irq0 fbfh 0 0 ie2 irq2 notes: 1. iex refers to all interrupt enable flags. 2. irqx refers to all interrupt request flags. 3. iex = "0" is interrupt disable mode. 4. iex = "1" is interrupt enable mode.
ks57c2408a/2416a microcontroller product specification september 1996 7?6 g electronics smsun g smsun interrupt priority each interrupt source can also be individually programmed to high levels by modifying the ipr register. when is1 = 0 and is0 = 1, a low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low-priority interrupt. if you clear the interrupt status flags (is1 and is0) to "0" in a interrupt service routine, a high-priority interrupt can be interrupted by low-priority interrupt (multi-level interrupt). before the ipr can be modified by 4-bit write instructions, all interrupts must first be disabled by a di instruction. when all interrupts are low priority (the lower three bits of the ipr register are "0"), the interrupt requested first will have high priority. therefore, the first-requested interrupt cannot be superseded by any other interrupt. if two or more interrupt requests are received simultaneously, the priority level is determined according to the standard interrupt priorities, where the default priority is assigned by hardware when the lower three ipr bits = "0". in this case, the higher-priority interrupt request is serviced and the other interrupt is inhibited. then, when the high-priority interrupt is returned from its service routine by an iret instruction, the inhibited service routine is started. table 7. interrupt priority register settings ipr.2 ipr.1 ipr.0 result of ipr bit setting 0 0 0 process all interrupt requests at low priority 0 0 1 intb and int4 0 1 0 int0 0 1 1 int1 1 0 0 ints 1 0 1 intt0 1 1 0 intt1 1 1 1 intad table 8. default priorities source default priority intb, int4 1 int0 2 int1 3 ints 4 intt0 5 intt1 6 intad 7 + programming tip ?setting the int interrupt priority set the int1 interrupt to high priority: bits emb smb 15 di ; ipr.3 (ime) ? 0 ld a,#3h ld ipr,a ei ; ipr.3 (ime) ? 1 external interrupts the external interrupt 0 and 1 mode registers (imod0 and imod1) are used to control the triggering edge of the input signal at the int0 and int1 pins. when a sampling clock rate of fxx/64 is used for int0, an interrupt request flag must be cleared before 16 machine cycles have elapsed. since the int0 pin has a clock-driven noise filtering circuit built into it, please take the following precautions when you use it: to trigger an interrupt, the input signal width at int0 must be at least two times wider than the pulse width of the clock selected by imod0. this is true even when the int0 pin is used for general-purpose input. since the int0 input sampling clock does not operate during stop or idle mode, you cannot use int0 to release power-down mode.
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7?7 september 1996 external interrupts (continued) when modifying the imod0 and imod1 registers, it is possible to accidentally set an interrupt request flag. to avoid unwanted interrupts, take these precautions when writing your programs: 1. disable all interrupts with a di instruction. 2. modify the imod0 or imod1 register. 3. clear all relevant interrupt request flags. 4. enable the interrupt by setting the appropriate iex flag. 5. enable all interrupts with an ei instruction. the external interrupt 2 (int2) mode register (imod2) is used to select int2 and ks pins as interrupt input. if a rising edge is detected at the int2 pin, or when a falling edge is detected at any one of the ks0?s7 pins, the irq2 flag is set to "1". this generates an interrupt request and a release signal for power-down mode. to generate a key interrupt on a falling edge at ks0- ks7, all ks0-ks7 pins must be configured to input mode. ks4-ks7, in particular, must always be set to input mode. if one or more of the pins which are configured as key interrupt (ks0?s7) are in low input or low output state, the key interrupt can not be occured. table 9. imod0 and imod1 register organization (4-bit w) imod0.3 0 imod0.1 imod0.0 effect of imod0 settings 0 select cpu clock for sampling 1 select fxx/64 sampling clock 0 0 0 rising edge detection 0 0 1 falling edge detection 0 1 0 both rising and falling edge detection 0 1 1 irq0 flag cannot be set to "1" 0 0 0 imod1.0 effect of imod1 settings 0000 rising edge detection 0001 falling edge detection table 10. imod2 register bit settings (4-bit w) 0 0 imod2.1 imod2.0 effect of imod2 settings 0000 select rising edge at int2 pin 0001 select falling edge at ks4?s7 0010 select falling edge at ks2?s7 0011 select falling edge at ks0?s7
ks57c2408a/2416a microcontroller product specification september 1996 7?8 g electronics smsun g smsun int2 ks7 ks6 ks5 ks4 ks3 ks2 ks1 ks0 rising edge detection circuit falling edge detection circuit imod2 clock selector irq2 to generate a key interrupt on a falling edge at ks0?s7, all ks0?s7 pins must be configured to input mode. ks4?s7, in particular, must always be configured to input mode. note: figure 18-1. circuit diagram for int2 and ks0-ks7
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7?9 september 1996 oscillator circuits the ks57c2408a/2416a microcontroller has two oscillator circuits: a main system clock circuit, and a subsystem clock circuit. the main system clock frequencies can be divided by 4, 8, or 64 by manipulating pcon bits 1 and 0. the system clock mode control register, scmod, lets you select the main system clock (fx) or a subsystem clock (fxt) as the cpu clock and to start (or stop) main system clock oscillation. the watch timer, buzzer and lcd display operate normally with a subsystem clock source, since they operate at very slow speeds and with very low power consumption (as low as 122 m s at 32.768 khz). note if a subsystem clock (fxt) is selected as the system clock, the microcontroller's analog-to-digital converter block does not operate. subsystem oscillator oscillator stop 1/4 cpu clock oscillator control circuit wait release signal internal reset signal power-down release signal pcon.2?con.3 clear fxt main system oscillator circuit xin xout frequency dividing circuit 1/2 1/16 selector selector scmod.3 scmod.0 pcon.0 pcon.1 pcon.2 pcon.3 fx watch timer fxx cpu stop signal (idle mode) lcd controller idle stop a/d converter watch timer basic timer timer/counters clock output circuit lcd controller xtin xtout figure 19. oscillator circuit diagram
ks57c2408a/2416a microcontroller product specification september 1996 7?0 g electronics smsun g smsun main system oscillator circuits xin xout figure 20. crystal/ceramic oscillator (fx) xin xout figure 21. external oscillator (fx) xin xout r figure 22. rc oscillator (fx) subsystem oscillator circuits 32.768 khz xtin xtout figure 23. crystal/ceramic oscillator (fxt) xtin xtout external clock figure 24. external oscillator (fxt)
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7?1 september 1996 power control register (pcon) the power control register, pcon, is used to select the cpu clock frequency and to control cpu operating and power-down modes. pcon bits 3 and 2 are controlled by the stop and idle instructions which engage the idle and stop power-down modes. idle and stop modes can be initiated by these instructions regardless of the current value of the enable memory bank flag (emb). table 11. power control register (pcon) organization (4-bit w) pcon bit settings resulting cpu operating mode pcon.3 pcon.2 0 0 normal cpu operating mode 0 1 idle power-down mode 1 0 stop power-down mode pcon bit settings resulting cpu clock frequency pcon.1 pcon.0 if scmod.0 = "0" if scmod.0 = "1" 0 0 fx/64 1 0 fx/8 1 1 fx/4 fxt/4 + programming tip ?setting the cpu clock to set the cpu clock to 0.95 m s at 4.19 mhz: bits emb smb 15 ld a,#3h ld pcon,a
ks57c2408a/2416a microcontroller product specification september 1996 7?2 g electronics smsun g smsun instruction cycle times the unit of time that equals one machine cycle varies depending on the main system clock is used, and on how the oscillator clock signal is divided (by 4, 8, or 64). table 12. instruction cycle times for cpu clock rates selected cpu clock resulting frequency oscillation source cycle time ( m s) fx/64 65.5 khz 15.3 fx/8 524.0 khz fx=4.19 mhz 1.91 fx/4 1.05 mhz 0.95 fxt/4 8.19 khz fxt=32.768 khz 122.0 system clock mode register (scmod) the system clock mode register, scmod, is used to select the cpu clock and to control main system clock oscillation. only its least significant and most significant bits can be manipulated by 1-bit write instructions. bits 2 and 1 in the scmod register are always logic zero. subsystem clock oscillation cannot, of course, be stopped internally. also, if you have selected fx as the cpu clock, setting scmod.3 to "1" will not stop main system clock oscillation. this can only be done by a stop instruction. table 13. system clock mode register (scmod) organization scmod register bit settings resulting clock selection scmod.3 scmod.0 cpu clock fx oscillation 0 0 fx on 0 1 fxt on 1 1 fxt off
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7?3 september 1996 switching the cpu clock together, bit settings in the power control register, pcon, and the system clock mode register, scmod, determine whether a main system or a subsystem clock is selected as the cpu clock. this makes it possible to switch dynamically between main and subsystem clocks and to modify operating frequencies. note a clock switch operation does not go into effect immediately when you make the scmod and pcon register modifications ?the previously selected clock continues to run for a certain number of machine cycles. for example, you are using the default cpu clock (normal operating mode and a main system clock of fx/64) and you want to switch from the fx clock to a subsystem clock and to stop the main system clock. to do this, you first need to set scmod.0 to "1". this switches the clock from fx to fxt but allows main system clock oscillation to continue. before the switch actually goes into effect, a certain number of machine cycles must elapse. after this time interval, you can disable main system clock oscillation by setting scmod.3 to "1". this same 'stepped' approach must be taken to switch from a subsystem clock to the main system clock: first, clear scmod.3 to "0" to enable main system clock oscillation. then, after a certain number of machine cycles have elapsed, select the main system clock by clearing all scmod values to logic zero. following a reset , cpu operation starts with the lowest main system clock frequency of 15.3 m s at 4.19mhz after the standard oscillation stabilization interval of 31.3 ms has elapsed. table 14 details the number of machine cycles that must elapse before a cpu clock switch modification goes into effect. table 14. elapsed machine cycles during cpu clock switch after scmod.0 = 0 scmod.0 = 1 before pcon.1 = 0 pcon.0 = 0 pcon.1 = 1 pcon.0 = 0 pcon.1 = 1 pcon.0 = 1 pcon.1 = 0 n/a 1 machine cycle 1 machine cycle n/a pcon.0 = 0 scmod.0 = 0 pcon.1 = 1 8 machine cycles n/a 8 machine cycles n/a pcon.0 = 0 pcon.1 = 1 16 machine cycles 16 machine cycles n/a fx / 4fxt pcon.0 = 1 scmod.0 = 1 n/a n/a fx / 4fxt (m/c) n/a notes : 1. even if oscillation is stopped by setting scmod.3 during main system clock operation, stop mode is not entered. 2. since the xin input is connected internally to v ss to avoid current leakage due to the crystal oscillator in stop mode, do not set scmod.3 to "1" when an external clock is used as the main system clock. 3. when the system clock is switched to the subsystem clock, it is necessary to disable any interrupts which may occur during the time intervals shown in table 14. 4. 'n/a' means 'not available'.
ks57c2408a/2416a microcontroller product specification september 1996 7?4 g electronics smsun g smsun + programming tip ?switching between main system and subsystem clock 1. switch from the main system clock to the subsystem clock: ma2sub bits scmod.0 ; switches to subsystem clock call dly80 ; delay 80 machine cycles bits scmod.3 ; stop the main system clock ret dly80 ld a,#0fh del1 nop nop decs a jr del1 ret 2. switch from the subsystem clock to the main system clock: sub2ma bitr scmod.3 ; start main system clock oscillation call dly80 ; delay 80 machine cycles bitr scmod.0 ; switch to main system clock ret clock output mode register (clmod) the clock output circuit is used to output clock pulses to the clo pin. the clock output mode register, clmod, is used to enable or disable clock output to the clo pin and to select the cpu clock source and frequency. to output a frequency, the clock output pin clo/p3.2 must be set to output mode and the latch for the pin must be cleared to "0". bit 2 in the clmod register must always be "0". table 15. clock output mode register (clmod) organization clmod bit settings resulting clock output clmod.1 clmod.0 clock source frequency 0 0 cpu clock (fx/4, fx/8, fx/64, fxt/4) 1.05 mhz, 524 khz, 65.5 khz, 8.19 khz 0 1 fxx/8 524 khz, 4.096 khz 1 0 fxx/16 262 khz, 2.048 khz 1 1 fxx/64 65.5 khz, 0.512 khz clmod.3 result of clmod.3 setting 0 clock output is disabled 1 clock output is enabled note : frequencies assume that fx is 4.19 mhz and fxt is 32.768 khz.
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7?5 september 1996 pm3.2 p3.2 output latch clo clmod.3 clmod.2 clmod.1 clmod.0 clock selector clocks 4 (fxx/8, fxx/16, fxx/64, cpu clock) figure 25. clo output pin circuit diagram + programming tip ?cpu clock output to the clo pin to output the cpu clock to the clo pin: bits emb ; or bitr emb smb 15 ld ea,#40h ld pmg2,ea ; p3.2 ? output mode bitr p3.2 ; clear p3.2 output latch ld a,#9h ld clmod,a
ks57c2408a/2416a microcontroller product specification september 1996 7?6 g electronics smsun g smsun power-down the ks57c2408a/2416a microcontroller has two power-down modes to reduce power consumption: idle and stop. in idle mode, the cpu clock stops while peripherals and the oscillator continue to operate normally. in stop mode, system clock oscillation is halted (assuming it is currently operating), and peripheral hardware components are powered-down. the effect of stop mode on specific peripheral component (cpu, basic timer, serial i/o, timer/ counters 0 and 1, watch timer, and lcd controller) and on external interrupt requests, is detailed in table 16. table 16. hardware operation during power-down modes operation stop mode (stop) idle mode (idle) system clock status can be changed only if the main system clock is used can be changed if the main system clock or subsystem clock is used clock oscillator main system clock oscillation stops cpu clock oscillation stops (main and subsystem clock oscillation continues) basic timer basic timer stops basic timer operates (with irqb set at each reference interval) serial interface operates only if external sck input is selected as the serial i/o clock operates if a clock other than the cpu clock is selected as the serial i/o clock timer/counter 0 operates only if tcl0 is selected as the counter clock timer/counter 0 is operational timer/counter 1 operates only if tcl1 is selected as the counter clock timer/counter 1 is operational watch timer operates only if subsystem clock (fxt) is selected as the counter clock watch timer is operational lcd controller operates only if a subsystem clock is selected as lcdck lcd controller is operational external interrupts int1, int2, and int4 are acknowledged; int0 is not serviced int1, int2, and int4 are acknowledged; int0 is not serviced cpu all cpu operations are disabled all cpu operations are disabled mode release signal interrupt request signals (except int0) are enabled by an interrupt enable flag or by reset input interrupt request signals (except int0 and intad) are enabled by an interrupt enable flag or by reset input a/d converter a/d converter is disabled a/d converter is disabled
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7?7 september 1996 + programming tip ?reducing power consumption for key input interrupt processing the following code shows real-time clock and interrupt processing for key inputs to reduce power consumption. in this example, the system clock source is switched from the main system clock to a subsystem clock and the lcd display is turned on: keyclk di call ma2sub ; main system clock ? subsystem clock switch subroutine smb 15 ld ea,#00h ld p4,ea ; all key strobe outputs to low level ld a,#3h ld imod2,a ; select ks0?s7 enable smb 0 bitr irqw bitr irq2 bits iew bits ie2 clks1 call watdis ; execute clock and display changing subroutine btstz irq2 jr cidle call sub2ma ; subsystem clock ? main system clock switch subroutine ei ret cidle idle ; engage idle mode nop nop jps clks1
ks57c2408a/2416a microcontroller product specification september 1996 7?8 g electronics smsun g smsun recommended connections for unused pins to reduce overall power consumption, please configure unused pins according to the guidelines described in table 17. table 17. unused pin connections for reduced power consumption pin/share pin names recommended connection p0.0 / sck p0.1 / so p0.2 / si p0.3 / btco input mode: connect to v dd output mode: do not connect p1.0 / int0 ?p1.2 / int2 connect to v dd p1.3 / int4 connect to v ss p2.0 / tcl0 p2.1 / tcl1 p2.2 p2.3 p3.0 / tclo0 p3.1 / tclo1 p3.2 / clo p3.3 / buz p4.0?4.3 p5.0?5.3 p6.0 / ks0 ?p6.3 / ks3 p7.0 / ks4 ?p7.3 / ks7 input mode: connect to v dd output mode: do not connect p9.0 / ad0 ?p9.3 / ad3 p10.0 / ad4 ?p10.1 / ad5 connect to v ss seg0?eg23 seg24 / p8.0 ?seg31 / p8.7 com0?om3 do not connect v lc0 ? lc2 connect to v ss bias if all of the v lc0 ? lc2 pins are unused, connect bias to v ss xt in connect xt in to v ss or v dd xt out do not connect test connect to v ss
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7?9 september 1996 reset table 18 provides detailed information about hardware register values after a reset occurs during power-down mode or during normal operation. table 18. hardware register values after reset hardware component or subcomponent if reset occurs during power-down mode if reset occurs during normal operation program counter (pc) lower five bits of address 0000h are transferred to pc12?, and the contents of 0001h to pc7?. lower five bits of address 0000h are transferred to pc12?, and the contents of 0001h to pc7?. program status word (psw) carry flag (c) retained undefined skip flag (sc0?c2) 0 0 interrupt status flags (is0, is1) 0 0 bank enable flags (emb, erb) bit 6 of address 0000h in program memory is transferred to the erb flag, and bit 7 of the address to the emb flag. bit 6 of address 0000h in program memory is transferred to the erb flag, and bit 7 of the address to the emb flag. stack pointer (sp) undefined undefined data memory (ram) registers e, a, l, h, x, w, z, y values retained (note1) undefined general-purpose registers values retained undefined bank selection registers (smb, srb) 0, 0 0, 0 bsc register (bsc0?sc3) 0 0 oscillator circuits power control register (pcon) 0 0 output mode register (clmod) 0 0 system clock control reg (scmod) 0 0 interrupts interrupt request flags (irqx) 0 0 interrupt enable flags (iex) 0 0 interrupt priority flag (ipr) 0 0 interrupt master enable flag (ime) 0 0 int0 mode register (imod0) 0 0 int1 mode register (imod1) 0 0 int2 mode register (imod2) 0 0 note1: the values of the 0f8h-0fdh are not retained when a reset signal is input.
ks57c2408a/2416a microcontroller product specification september 1996 7?0 g electronics smsun g smsun table 18. hardware register values after reset (continued) hardware component or subcomponent if reset occurs during power-down mode if reset occurs during normal operation i/o ports output buffers off off output latches 0 0 port mode flags (pm) 0 0 pull-up resistor mode reg (pumod) 0 0 basic timer count register (bcnt) undefined undefined mode register (bmod) 0 0 basic timer output enable flag (boe) 0 0 tc0, tc1 count registers (tcnt0/1) 0 0 reference registers (tref0/1) ffh, ffffh ffh, ffffh mode registers (tmod0/1) 0 0 t/c output enable flags (toe0/1) 0 0 watch timer watch timer mode register (wmod) 0 0 lcd controller/driver lcd mode register (lmod) 0 0 lcd control register (lcon) 0 0 display data memory values retained undefined output buffers off off a/d converter a/d mode register (admod) 0 0 a/d data register 0 0 serial i/o interface sio mode register (smod) 0 0 sio interface buffer (sbuf) values retained undefined
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7?1 september 1996 i/o ports the ks57c2408a/2416a microcontroller has eleven i/o ports. there are 10 input pins, 12 output pins, 20 configurable i/o pins, and 8 n-channel open-drain i/o pins, for a total of 50 i/o pins. port mode flags (pm flags) port mode flags (pm) are used to configure ports 0 and 2? to input or output mode by setting or clearing the corresponding i/o buffer. if a pm bit = "0", the corresponding i/o pin is set to input mode. if the pm bit = "1", the pin is set to output mode. table 19. port mode group flags (8-bit w) pm group id address bit 3 bit 2 bit 1 bit 0 pmg1 fe8h pm0.3 pm0.2 pm0.1 pm0.0 fe9h pm7 "0" pm5 pm4 pmg2 feah pm2.3 pm2.2 pm2.1 pm2.0 febh pm3.3 pm3.2 pm3.1 pm3.0 pmg3 fech pm6.3 pm6.2 pm6.1 pm6.0 fedh "0" "0" "0" "0" note: if a pm bit = "0", the corresponding i/o pin is set to input mode. if bit = "1", the pin is set to output mode. all flags are cleared to "0" by reset . + programming tip ?configuring i/o ports as input or output the following instructions configure p0.3 and p2 to output and the remaining ports to input: bits emb smb 15 ld ea,#08h ld pmg1,ea ; p0.3 ? output, p0.0?.2, p4, p5, p7 ? input ld ea,#0fh ld pmg2,ea ; p2.0?.3 ? output, p3.0?.3 ? input ld ea,#00h ld pmg3,ea ; p6.0?.3 ? input
ks57c2408a/2416a microcontroller product specification september 1996 7?2 g electronics smsun g smsun pull-up resistor mode registers the pull-up resistor mode register (pumod) is used to assign internal pull-up resistors to specific i/o ports. when a pumod bit = "1", a pull-up resistor is assigned to the corresponding i/o port: pumod.3 for port 3, pumod.2 for port 2, and so on. i/o ports 4 and 5 are an exception, as these port pins may only be assigned internal pull-up resistors via mask option. pumod bits 4 and 5 should always be cleared to logic zero. when a configurable i/o port pin is used as an output pin, its assigned pull-up resistor is automatically disabled, even though the pin's pull-up may be enabled by a corresponding pumod bit setting. table 20. pull-up resistor mode register (pumod) organization (8-bit w) address bit 3 bit 2 bit 1 bit 0 fdch pumod.3 pumod.2 pumod.1 pumod.0 fddh pumod.7 pumod.6 "0" "0" + programming tip ?enabling and disabling i/o port pull-up resistors p6 and p7 enable pull-up resistors, p0?3 disable pull-up resistors. bits emb smb 15 ld ea,#0c0h ld pumod,ea ; p6 and p7 enable pin addressing for output port 8 the addresses for the port 8 1-bit output pin buffers are located in bank 1 of data memory instead of bank 15. to address port 8 output pins, use the settings emb = 1 and smb = 1. the lcd mode register, lmod is used to control whether the pin address is used for lcd data output or for normal data output.
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7?3 september 1996 port 0 circuit diagram sck p0.0/ sck p0.1/so p0.2/si sck so si p0.2 latch p0.1 latch p0.0 latch btco p0.3/btco p0.3 latch pm0.2 pm0.3 pm0.1 pm0.0 v dd pumod.0 when a port pin acts as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings to the pull-up resistor mode register (pumod). note: smod.5 smod.7 smod.6 figure 26. port 0 circuit diagram
ks57c2408a/2416a microcontroller product specification september 1996 7?4 g electronics smsun g smsun port 1 circuit diagram int0 int1 int2 int4 p1.0 pumod.1 p1.1 p1.2 p1.3 v dd v dd v dd n/r circuit n/r = noise reduction imod0.3 figure 27. port 1 circuit diagram
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7?5 september 1996 port 2, 3, 6 circuit diagram px.0 px.1 px.2 px.3 output latch m u x 1, 4, 8 1, 4, 8 pmx.2 pmx.3 pmx.1 pmx.0 v dd pumod.x x = port number (2, 3, 6) when a port pin acts as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings to the pull-up resistor mode register (pumod). the 8?it access is impossible at port 2 and 3. note: figure 28. port 2, 3, and 6 circuit diagram
ks57c2408a/2416a microcontroller product specification september 1996 7?6 g electronics smsun g smsun port 4, 5 circuit diagram px.0 px.1 px.2 px.3 v dd v dd v dd pmx output latch m u x v dd mask option n-channel open-drain 1, 4, 8 1, 4, 8 8 x = 4 and 5 (port 4 and port 5) figure 29. port 4 and 5 circuit diagram
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7?7 september 1996 port 7 circuit diagram p7.0 p7.1 p7.2 p7.3 v dd pm7 output latch m u x v dd v dd v dd 8 1, 4 pumod.7 when a port pin acts as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings to the pull-up resistor mode register (pumod). note: 1, 4 figure 30. port 7 circuit diagram
ks57c2408a/2416a microcontroller product specification september 1996 7?8 g electronics smsun g smsun basic timer (bt) the basic timer generates interrupt requests at precise intervals. you can use the basic timer as a "watchdog" timer for monitoring system events or use bt output to stabilize clock oscillation when stop mode is released by an interrupt and following reset . interval timer function the measurement of elapsed time intervals is the basic timer's primary function. the standard interval is 256 bt clock pulses. to restart the basic timer, set bit 3 of the mode register bmod to "1". the 8-bit counter register, bcnt, is incremented each time a clock signal is detected that corresponds to the frequency selected by bmod. bcnt continues incrementing as it counts bt clocks until an overflow occurs. an overflow causes the bt interrupt request flag (irqb) to be set to "1" to signal that the designated time interval has elapsed. an interrupt request is then generated, bcnt is cleared to "0", and counting continues from 00h. watchdog timer function the basic timer can also be used as a "watchdog" timer to signal the occurrence of specific system events. each time bcnt overflows, an overflow signal is sent to the basic timer clock output pin, btco. to enable btco output operation, clear the output latch for pin p0.3 to "0" and set the port mode flag for p0.3 (pm0.3) to "1". oscillation stabilization interval control setting bits 2? of the bmod register determines the time interval (also referred to as 'wait time') required to stabilize clock signal oscillation when power-down mode is released by an interrupt. when a reset signal is generated , the standard stabilization interval for system clock oscillation following a reset is 31.3ms at 4.19 mhz. "clear" signal bits instruction bmod.3 bmod.2 bmod.1 bmod.0 clock selector bcn t irqb interrupt request overflow cpu clock start signal (power-down release) 1-bit r/w clock inpu t clear irqb clear bcnt boe btco / p0.3 p0.3 latch 4 8 (fxx/2 12 , fxx/2 9 , fxx/2 7 , fxx/2 5) figure 31. basic timer circuit diagram
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7?9 september 1996 basic timer mode register (bmod) the basic timer mode register, bmod, is used to select input frequency and oscillation stabilization time. the most significant bit of the bmod register, bmod.3, is used to start the basic timer again. when bmod.3 is set to "1", the contents of the bt counter register (bcnt) and the bt interrupt request flag (irqb) are both cleared to "0", and timer operation is restarted. table 21. basic timer mode register (bmod) organization bmod.3 basic timer restart bit 1 restart basic timer; clear irqb, bcnt, and bmod.3 to "0" bmod.2 bmod.1 bmod.0 basic timer input clock oscillation stabilization 000 fxx/2 12 (1.02 khz) 2 20 /fxx (250 ms) 011 fxx/2 9 (8.18 khz) 2 17 /fxx (31.3 ms) 101 fxx/2 7 (32.7 khz) 2 15 /fxx (7.82 ms) 111 fxx/2 5 (131 khz) 2 13 /fxx (1.95 ms) notes : 1. clock frequencies and stabilization intervals assume a system oscillator clock frequency (fxx) of 4.19 mhz. 2. fxx = selected system clock frequency. 3. oscillation stabilization time is the time required to stabilize clock signal oscillation after stop mode is released. the data in the table column 'oscillation stabilization' can also be interpreted as "interrupt interval time." 4. the standard stabilization time for system clock oscillation following a reset is 31.3 ms at 4.19 mhz. basic timer counter (bcnt) bcnt is an 8-bit counter register for the basic timer. when bcnt has incremented to hexadecimal 'ffh', it is cleared to '00h' and an overflow is generated. the overflow causes the interrupt request flag, irqb, to be set to "1". when the interrupt request is generated, bcnt immediately resumes counting incoming clock signals. note always execute a bcnt read operation twice to eliminate the possibility of reading unstable data while the counter is incrementing. if, after two consecutive reads, the bcnt values match, you can select the latter value as valid data. until the results of the consecutive reads match, however, the read operation must be repeated until the validation condition is met. basic timer output enable flag (boe) the boe flag value enables and disables basic timer output to the btco/p0.3. when boe is "0", basic timer output to the btco pin is disabled; when it is "1", bt output to the btco pin is enabled. f92h 1-bit r/w toe1 toe0 boe 0
ks57c2408a/2416a microcontroller product specification september 1996 7?0 g electronics smsun g smsun + programming tip ?using the basic timer 1. to read the basic timer count register (bcnt): bits emb smb 15 bcntr ld ea,bcnt ld yz,ea ld ea,bcnt cpse ea,yz jr bcntr 2. when stop mode is released by an interrupt, set the oscillation stabilization interval to 31.3 ms: bits emb smb 15 ld a,#0bh ld bmod,a ; wait time is 31.3 ms stop ; set stop power-down mode nop nop normal operating mode stop mode idle mode (31.3 ms) cpu operation stop instruction stop mode is released by interrupt normal operating mode 3. to set the basic timer interrupt interval time to 1.95 ms (at 4.19 mhz): bits emb smb 15 ld a,#0fh ld bmod,a ei bits ieb ; basic timer interrupt enable flag is set to "1" 4. clear bcnt and the irqb flag and restart the basic timer: bits emb smb 15 bits bmod.3
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7?1 september 1996 8-bit timer/counter 0 (tc0) timer/counter 0 (tc0) is used to count system 'events' by identifying the transition (high-to-low or low-to-high) of incoming square wave signals. to indicate that an event has occurred, or that a specified time interval has elapsed, tc generates an interrupt request. by counting signal transitions and comparing the current counter value with the reference register value, tc can be used to measure specific time intervals. timer/counter 0 can supply a clock signal to the clock selector circuit of the serial i/o interface for data shifter and clock counter operations. (these internal sio operations are controlled in turn by the sio mode register, smod). this clock generation function lets you adjust data transmission rates across the serial interface. tcl0 tclo0 serial i/o clock selector tcnt0 8-bit comparator p2.0 tol0 p3.0 latch toe0 irqt0 pm3.0 tmod0.7 tmod0.6 tmod0.5 tmod0.4 tmod0.3 tmod0.2 tmod0.1 tmod0.0 tref0 8 8 8 clear inverted clear set clear clocks (fxx/2 , fxx/2 , fxx/2 , fxx) 10 64 figure 32. tc0 circuit diagram
ks57c2408a/2416a microcontroller product specification september 1996 7?2 g electronics smsun g smsun programmable timer/counter function timer/counter 0 can be programmed to generate interrupt requests at various intervals based on the selected system clock frequency. its 8-bit tc0 mode register tmod0 is used to activate the timer/counter and to select the clock frequency. the reference register tref0 stores the value for the number of clock pulses to be generated between interrupt requests. the counter register, tcnt0, counts the incoming clock pulses, which are compared to the tref0 value as tcnt0 is incremented. when there is a match (tref0 = tcnt0), the tc0 interrupt request flag (irqt0) is set to logic one, the status of tol0 is inverted, and the interrupt is generated. the content of tcnt0 is then cleared to 00h and tc0 continues counting. tc0 event counter function timer/counter 0 can monitor or detect system 'events' by using the external clock input at the tcl0 pin as the counter source. with the exception of the different tmod0.4?mod0.6 settings, the operation sequence for tc0's event counter function is identical to its programmable timer/counter function. to activate the tc0 event counter function, p2.0/tcl0 must be set to input mode. using timer/counter 0, a modifiable clock frequency can be output to the tc0 clock output pin, tclo0. to enable the output to the tclo0/p3.0, the i/o mode flag for p3.0 (pm3.0) must be set to output mode and output latch value for p3.0 must be cleared to "0" after the timer output enable flag (toe0) is set to "1". + programming tip ?tc0 signal output to the tclo0 pin output a 30 ms pulse width signal to the tclo0 pin: bits emb smb 15 ld ea,#79h ld tref0,ea ld ea,#4ch ld tmod0,ea ld ea,#10h ld pmg2,ea ; p3.0 ? output mode bitr p3.0 ; p3.0 clear bits toe0
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7?3 september 1996 + programming tip ?external tcl0 clock output to the tclo0 pin output external tcl0 clock pulse to the tclo0 pin (divided by four): external (tcl0) clock pulse tclo0 output pulse bits emb smb 15 ld ea,#01h ld tref0,ea ld ea,#0ch ld tmod0,ea ld ea,#10h ld pmg2,ea ; p3.0 ? output mode bitr p3.0 ; p3.0 clear bits toe0 tc0 mode register (tmod0) tmod0 is the 8-bit mode control register for timer/counter 0. when tmod0.3 is set to "1", the contents of tcnt0, irqt0, and tol0 are cleared, counting starts from 00h, and tmod0.3 is automatically reset to "0" for normal tc0 operation. when tc0 operation stops (tmod0.2 = "0"), the contents of the tc0 counter register tcnt0 are retained until tc0 is re-enabled. table 22. tc0 mode register (tmod0) organization bit name setting resulting tc0 function address tmod0.7 0 always logic zero tmod0.6 f91h tmod0.5 0,1 specify input clock edge and internal frequency tmod0.4 tmod0.3 1 clear tcnt0, irqt0, and tol0; then resume counting. (this bit is automatically cleared to "0" when counting resumes.) tmod0.2 0 disable timer/counter 0; retain tcnt0 contents f90h 1 enable timer/counter 0 tmod0.1 0 always logic zero tmod0.0 0 always logic zero
ks57c2408a/2416a microcontroller product specification september 1996 7?4 g electronics smsun g smsun table 23. tmod0.6, tmod0.5, and tmod0.4 bit settings tmod0.6 tmod0.5 tmod0.4 resulting counter source and clock frequency 0 0 0 external clock input (tcl0) on rising edges 0 0 1 external clock input (tcl0) on falling edges 100 fxx/2 10 (4.09 khz) 101 fxx /2 6 (65.5 khz) 110 fxx/2 4 (262 khz) 1 1 1 fxx = 4.19 mhz note : 'fxx' = selected system clock of 4.19 mhz. + programming tip ?restarting tc0 counting operation 1. set tc0 timer interval to 4.09 khz: bits emb smb 15 ld ea,#4ch ld tmod0,ea ei bits iet0 2. clear tcnt0, irqt0, and tol0; then restart tc0 counting operation: bits emb smb 15 bits tmod0.3 tc0 reference register (tref0) tref0 is used to store a reference value to be compared to the incrementing tcnt0 register in order to identify an elapsed time interval. use the following formula to calculate the correct value to load to the tref0 reference register: tc0 timer interval = (tref0 value + 1) 1 tmod0frequencysetting assuming tref0 value 1 0 tc0 output enable flag (toe0) the 1-bit timer/counter 0 output enable flag toe0 controls output from timer/counter 0 to the tclo0 pin. f92h 1-bit r/w toe1 toe0 boe "0" when you set the toe0 flag to "1", the contents of tol0 can be output to the tclo0 pin.
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7?5 september 1996 + programming tip ?setting a tc0 timer interval to set a 30 ms timer interval for tc0, given fx = 4.19 mhz, follow these steps. 1. select the timer/counter 0 mode register with a maximum setup time of 62.5 ms (assume that the tc0 counter clock = fx/2 10 , and tref0 is set to ffh): 2. calculate the tref0 value: 30 ms = tref0value+1 4.09khz tref0 + 1 = 30ms 244 m s = 122.9 = 7ah tref0 value = 7ah ?1 = 79h 3. load the value 79h to the tref0 register: bits emb smb 15 ld ea,#79h ld tref0,ea ld ea,#4ch ld tmod0,ea
ks57c2408a/2416a microcontroller product specification september 1996 7?6 g electronics smsun g smsun 16-bit timer/counter (tc1) timer/counter 1 (tc1) is used to count system 'events' by identifying the transition (high-to-low or low-to-high) of incoming square wave signals. to indicate that an event has occurred, or that a specified time interval has elapsed, tc1 generates an interrupt request. by counting signal transitions, it can be used to measure time intervals. the tc1 circuit also has 16-bit comparator logic. tc1 has a reloadable counter that consists of two parts: a 16-bit reference register (tref1) into which you can write data for use as a reference value, and a 16-bit counter register (tcnt1) whose contents are automatically incremented by counter logic. the only functional differences between tc0 and tc1 are the size of the counter and reference value registers (8-bit versus 16-bit), and that only tc0 can generate a clock signal for the serial i/o interface. tcl1 tclo1 clock selector tcnt1 16-bit comparator p2.1 tol1 p3.1 latch toe1 irqt1 pm3.1 tref1 16 16 8 tmod1.7 tmod1.6 tmod1.5 tmod1.4 tmod1.3 tmod1.2 tmod1.1 tmod1.0 clear inverted set clear clear clocks (fxx/2 , fxx/2 , fxx/2 , fxx/2 ) 10 86 4 figure 33. timer/counter 1 circuit diagram
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7?7 september 1996 programmable timer/counter function timer/counter 1 can be programmed to generate interrupt requests at variable intervals, based on the system clock frequency you select. the 8-bit tc1 mode register, tmod1, is used to activate the timer/counter and to select the clock frequency; the 16-bit reference register, tref1, is used to store the value for the desired number of clock pulses between interrupt requests. the 16-bit counter register, tcnt1, counts the incoming clock pulses, which are compared to the tref1 value. when there is a match, the tc1 interrupt request flag (irqt1) is set to logic one, the status of tol1 is inverted, and the interrupt is output. the content of tcnt1 is then cleared to 0000h, and tc1 continues counting. tc1 event counter function timer/counter 1 can monitor system 'events' by using the external clock input at the tcl1 pin (i/o port 2.1) as the counter source. with the exception of the different tmod1.4?mod1.6 settings, the operation sequence for tc1's event counter function is identical to its programmable timer/counter function. to activate the tc1 event counter function, p3.3/tcl1 must be set to input mode. using timer/counter 1, a modifiable clock frequency can be output to the tc1 clock output pin, tclo1. to enable the output to the tclo1/p3.1, p3.1 must be set to output mode and the latch for p3.1 must be cleared to "0" when timer output enable flag (toe1) has been set to "1". + programming tip ?tc1 signal output to the tclo1 pin output a 30 ms pulse width signal to the tclo1 pin: bits emb smb 15 ld ea,#79h ld tref1a,ea ld ea,#00h ld tref1b,ea ld ea,#4ch ld tmod1,ea ld ea,#02h ld pmg2,ea ; p3.1 ? output mode bitr p3.1 ; p3.1 clear bits toe1
ks57c2408a/2416a microcontroller product specification september 1996 7?8 g electronics smsun g smsun + programming tip ?external tcl1 clock output to the tclo1 pin output the external tcl1 clock source to the tclo1 pin (divide by four): external (tcl1) clock pulse tclo1 output pulse bits emb smb 15 ld ea,#01h ld tref1a,ea ld ea,#00h ld tref1b,ea ld ea,#0ch ld tmod1,ea ld ea,#02h ld pmg2,ea ; p3.1 ? output mode bitr p3.1 ; p3.1 clear bits toe1 tc1 mode register (tmod1) tmod1 is the 8-bit mode register for timer/counter 1. when tmod1.3 is set to "1", the contents of tcnt1, irqt1, and tol1 are cleared, counting starts from 0000h, and tmod1.3 is automatically reset to "0" for normal tc1 operation. when tc1 operation stops (tmod1.2 = "0"), the contents of the tc1 counter register, tcnt1, are retained until tc1 is re-enabled. table 24. tc1 mode register (tmod1) organization bit name setting resulting tc1 function address tmod1.7 0 always logic zero tmod1.6 fa1h tmod1.5 0,1 specify input clock edge and internal frequency tmod1.4 tmod1.3 1 clear tcnt1, irqt1, and tol1 and resume counting immediately (this bit is automatically cleared to logic zero immediately after counting resumes.) tmod1.2 0 disable timer/counter 1; retain tcnt1 contents fa0h 1 enable timer/counter 1 tmod1.1 0 always logic zero tmod1.0 0 always logic zero
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7?9 september 1996 table 25. tmod1.6, tmod1.5, and tmod1.4 bit settings tmod1.6 tmod1.5 tmod1.4 resulting counter source and clock frequency 0 0 0 external clock input (tcl1) on rising edges 0 0 1 external clock input (tcl1) on falling edges 100 fxx/2 10 = 4.09 khz 101 fxx /2 8 = 16.4 khz 110 fxx/2 6 = 65.5 khz 111 fxx/2 4 = 262 khz note : 'fxx' = selected system clock of 4.19 mhz. + programming tip ?restarting tc1 counting operation 1. set tc1 timer interval to 4.09 khz: bits emb smb 15 ld ea,#4ch ld tmod1,ea ei bits iet1 2. clear tcnt1, irqt1, and tol1; then restart tc1 counting operation: sbits emb smb 15 bits tmod1.3 tc1 reference register (tref1) the tc1 reference register tref1 is a 16-bit write- only register that is mapped to ram locations fa8h fa9h (tref1a) and faah?abh (tref1b). it is addressable by 8-bit ram control instructions. use the following formula to calculate the correct value to load to the tref1 reference register: tc1 timer interval = (tref1 value + 1) 1 tmod1frequencysetting assuming tref1 value 1 0 tc1 output enable flag (toe1) the 1-bit timer/counter 1 output enable flag toe1 controls output from timer/counter 1 to the tclo1 pin. f92h 1-bit r/w toe1 toe0 boe 0 when you set the toe1 flag to "1", the contents of tol1 can be output to the tclo1 pin.
ks57c2408a/2416a microcontroller product specification september 1996 7?0 g electronics smsun g smsun + programming tip ?setting a tc1 timer interval to set a 30 ms timer interval for tc1, given fxx = 4.19 mhz, follow these steps. 1. select the timer/counter 1 mode register with a maximum setup time of 16 seconds; assume the tc1 counter clock = fxx/2 10 and tref1 is set to ffffh. 2. calculate the tref1 value: 30 ms = tref1value+1 4.09khz tref1 + 1 = 30ms 244 m s = 122.9 = 7ah tref1 value = 7ah ?1 = 79h 3. load the value 79h to the tref1 register: bits emb smb 15 ld ea,#79h ld tref1a,ea ld ea,#00h ld tref1b,ea ld ea,#4ch ld tmod1,ea
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7?1 september 1996 watch timer watch timer functions include real-time and watch- time measurement and interval timing for the system clock. to start watch timer operation, set bit 2 of the watch timer mode register, wmod.2, to "1". the watch timer starts, the interrupt request flag irqw is automatically set to "1", and interrupt requests commence in 0.5-second intervals. because the watch timer generates a quasi-interrupt instead of a vectored interrupt, the irqw flag should be cleared to "0" by program software as soon as a requested interrupt service routine has executed. the watch timer can generate a steady 2 khz, 4 khz, 8 khz, or 16 khz signal to the buz pin. to generate a buz signal, the output latch for i/o port 3.3 is cleared to "0" and the port 3.3 output mode flag (pm3.3) set to 'output' mode. by setting wmod.1 to "1", the watch timer will function in high-speed mode, generating an interrupt every 3.91 ms. high-speed mode is useful for timing events for program debugging sequences. the watch timer supplies the clock frequency for the lcd controller (f lcd ). therefore, if the watch timer is disabled, the lcd controller does not operate. fx = main system clock fxt = subsystem clock fw = watch timer frequency wmod.7 wmod.6 wmod.5 wmod.4 wmod.3 wmod.2 wmod.1 wmod.0 8 p3.3 latch pm3.3 frequency dividing circuit selector circuit irqw fxt fx/128 fw 32.768 khz buz mux fw/2 7 fw/2 (512 hz) 6 fw/2 (2 hz) 14 enable / disable clock selector lcd f fw/16 (2 khz) fw/8 (4 khz) fw/4 (8 khz) fw/2 (16 khz) figure 34. watch timer circuit diagram
ks57c2408a/2416a microcontroller product specification september 1996 7?2 g electronics smsun g smsun watch timer mode register (wmod) the watch timer mode register wmod is used to select specific watch timer operations. table 26. watch timer mode register (wmod) organization (8-bit w) bit name values function address wmod.7 0 disable buzzer (buz) signal output 1 enable buzzer (buz) signal output wmod.6 0 always logic zero wmod.5 ?.4 0 0 2 khz buzzer (buz) signal output f89h 0 1 4 khz buzzer (buz) signal output 1 0 8 khz buzzer (buz) signal output 1 1 16 khz buzzer (buz) signal output wmod.3 0 input level to xt in pin is low (read-only bit) 1 input level to xt in pin is high (read-only bit) wmod.2 0 disable watch timer; clear frequency dividing circuits 1 enable watch timer f88h wmod.1 0 normal mode; sets irqw to 0.5 s 1 high-speed mode; sets irqw to 3.91 ms wmod.0 0 select (fx/128 ) as the watch timer clock (fw) 1 select subsystem clock as watch timer clock (fw) note : main system clock frequency (fx) is assumed to be 4.19 mhz; subsystem clock (fxx) is assumed to be 32.768 khz. + programming tip ?using the watch timer 1. select a subsystem clock as the lcd display clock, a 0.5 second interrupt, and 2 khz buzzer enable: bits emb smb 15 ld ea,#80h ld pmg2,ea ; p3.3 ? output mode bitr p3.3 ld ea,#85h ld wmod,ea bits iew 2. sample real-time clock processing method: clock btstz irqw ; 0.5 second check ret ; no, return ; yes, 0.5 second interrupt generation ; increment hour, minute, second
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7?3 september 1996 lcd controller/driver the ks57c2408a/2416a microcontroller can directly drive an up-to-12-digit (96-segment) lcd panel. data written to the lcd display ram can be transferred to the segment signal pins automatically without program control. when a subsystem clock is selected as the lcd clock source, the lcd display is enabled even during stop and idle modes. lcd ram address area ram addresses 1e8h?ffh are used as lcd data memory. these locations can be addressed by 1-bit or 4-bit instructions. when the bit value of a display segment is "1", the lcd display is turned on; when the bit value is "0", the display is turned off. display ram data are sent out through segment pins seg0?eg23 using a direct memory access (dma) method that is synchronized with the f lcd signal. ram addresses in this location that are not used for lcd display can be allocated to general-purpose use. p8.0 p8.1 p8.2 p8.3 p8.4 p8.5 p8.6 p8.7 p8.8 p8.9 p8.10 p8.11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 1f4h 1f5h 1f6h 1f7h 1f8h 1f9h 1fah 1fbh 1fch 1fdh 1feh 1ffh bit3 bit2 bit1 com3 com2 com1 com0 1e8h 1e9h bit0 seg0 seg1 ...... ...... ...... ...... ...... figure 35. lcd display data ram organization
ks57c2408a/2416a microcontroller product specification september 1996 7?4 g electronics smsun g smsun 1ffh.3 1ffh.2 1ffh.1 1ffh.0 1f4h.3 1f4h.2 1f4h.1 1f4h.0 1e8h.3 1e8h.2 1e8h.1 1e8h.0 seg23/p8.11 seg22/p8.10 seg17/p8.5 seg16/p8.4 seg15/p8.3 seg11 ... seg0 com3 com2 com1 com0 v lc0 v lc1 v lc2 timing controller lmod lcon m u x m u x m u x s e l s e l s e g m e n t d r i v e r com control lcd voltage control 8 4 4 4 4 lcd f seg21/p8.9 seg20/p8.8 seg19/p8.7 seg18/p8.6 seg14/p8.2 seg13/p8.1 seg12/p8.0 figure 36. lcd circuit diagram
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7?5 september 1996 lcd control register (lcon) the lcon register is used to turn the lcd display on and off and to control the flow of current to dividing resistors in the lcd circuit. when lcon.0 is "0", the lcd display is turned off and the current to the dividing resistors is cut off, regardless of the current lmod.3 value. table 27. lcd control register (lcon) organization (4-bit w) lcon bit setting description lcon.3 0 this bit is used for internal testing only; always logic zero. lcon.2 0 always logic zero. lcon.1 0 always logic zero. lcon.0 0 lcd output low; turn display off, cut off current to dividing resistors, and output port 8 latch contents. 1 if lmod.3 = "0": lcd output low; turn display off; output port 8 latch contents; if lmod.3 = "1": com and seg output in display mode; turn display on. table 28. relationship of lcon.0 and lmod.3 bit settings lcon.0 lmod.3 com0-com3 seg0-seg23 p8.0-p8.11 0 x output low; lcd display off output low; lcd display off output latch contents; cut off current to dividing resistors 1 0 output low; lcd display off output low; lcd display off output latch contents; lcd display off 1 com output corresponds to display mode seg output corresponds to display mode output latch contents; lcd display on note :' x ' means 'don't care.' table 29. lcd clock signal (lcdck) frame frequency lcdck frequency static 1/2 duty 1/3 duty 1/4 duty fw/2 9 (64 hz) 64 32 21 16 fw/2 8 (128 hz) 128 64 43 32 fw/2 7 (256 hz) 256 128 85 64 fw/2 6 (512 hz) 512 256 171 128 notes : 1. 'fw' is the watch timer clock frequency of 32.768 khz. 2. the watch timer clock frequency for lcdck is shown in parentheses in column one.
ks57c2408a/2416a microcontroller product specification september 1996 7?6 g electronics smsun g smsun lcd mode register (lmod) the lcd mode register lmod is used to control lcd controller. because the lcd clock (lcdck) is generated by dividing the watch timer clock (fw), the watch timer must be enabled when the lcd display is turned on. the lcd display can continue to operate during idle and stop modes if a subsystem clock is used as the watch timer source. table 30. lcd mode control register (lmod) organization lmod.7 lmod.6 lcd output segments and 1-bit output pins 0 0 segments 12?5, 16?9, and 20?3 0 1 segments 12?5 and 16?9; 1-bit output at p8.8?8.11 1 0 segments 12?5; 1-bit output at p8.4?8.7 and p8.8?8.11 1 1 1-bit output only at p8.0?8.3, p8.4?8.7, and p8.8?8.11 lmod.5 lmod.4 lcd clock (lcdck) frequency 00 32.768 khz watch timer clock (fw)/2 9 = 64 hz 01 fw/2 8 = 128 hz 10 fw/2 7 = 256 hz 11 fw/2 6 = 512 hz lmod.3 lmod.2 lmod.1 lmod.0 duty and bias selection for lcd display 0 x x x lcd display off 1000 1/4 duty, 1/3 bias 1001 1/3 duty, 1/3 bias 1010 1/2 duty, 1/2 bias 1011 1/3 duty, 1/2 bias 1100 static note :' x ' means 'don't care.' table 31. maximum number of display digits per duty cycle lcd duty lcd bias com output pins maximum digit display ( 8 segment pins) static static com0 3 1/2 1/2 com0?om1 6 1/3 1/2 com0?om2 9 1/3 1/3 com0?om2 9 1/4 1/3 com0?om3 12
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7?7 september 1996 lcon.0 v lc0 v lc1 v lc2 v lcd = 3 v v lc3 v dd v ss 2 r r r r bias pin static and 1/3 bias (v lcd = 3 v at v dd = 5 v) 1/2 bias (v lcd = 2.5 v at v dd = 5v ) lcon.0 v lc0 v lc1 v lc2 v lcd = 2.5 v v lc3 v dd v ss 2 r r r r bias pin r = optional voltage dividing resistor r ' = external resistor static and 1/3 bias (v lcd = 5 v at v dd = 5v) lcon.0 v lc0 v lc1 v lc2 v lcd = 5 v v lc3 v dd v ss 2 r r r r bias pin voltage dividing resistor adjustment 2r ' r ' r ' r ' lcon.0 v lc0 v lc1 v lc2 v lcd v lc3 v dd v ss 2r r r r bias pin figure 37. voltage dividing resistor circuit diagrams
ks57c2408a/2416a microcontroller product specification september 1996 7?8 g electronics smsun g smsun lcd drive voltage the lcd display is turned on only when the voltage difference between the common and segment signals is greater than v lcd . the lcd display is turned off when the difference between the common and segment signal voltages is less than v lcd . note the lcd panel display may deteriorate if a dc voltage is applied that lies between the common and segment signal voltage. therefore, always drive the lcd panel with ac voltage. lcd voltage dividing resistors on-chip voltage dividing resistors for the lcd circuit can be configured by mask option selection. using these optional internal voltage dividing resistors, you can drive either a 3-volt or a 5-volt lcd display using external biasing. bias pins are connected externally to the v lcd pin so that it can handle the different lcd drive voltages. to cut off the current supply to the voltage dividing resistors, clear lcon.0 when you turn the lcd display off. common (com) signals the common signal output pin selection (com pin selection) varies according to the selected duty cycle. table 32. common signal pins used per duty cycle display mode com0 pin com1 pin com2 pin com3 pin static selected n/c n/c n/c 1/2 duty selected selected n/c n/c 1/3 duty selected selected selected n/c 1/4 duty selected selected selected selected note : 'nc' means that no connection is required. v ss com0 v lc0 v lcd tf = t t : lcdck tf : frame frequency figure 38. lcd common signal waveform (static)
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7?9 september 1996 com0,1 (1/2 duty) tf = 2 t tf = 3 t v ss v ss com0,1 (1/3 duty) v lc0 v lc1, 2 v lcd v lc0 v lc1, 2 v lcd t : lcdck tf : frame frequency figure 39. lcd common signal waveforms at 1/2 bias (1/2, 1/3 duty) tf = 4 t tf = 3 t v ss v ss com0? (1/3 duty) com0? (1/4 duty) v lc0 v lc1 v lc2 v lc0 v lc1 v lc2 v lcd v lcd t : lcdck tf : frame frequency figure 40. lcd common signal waveforms at 1/3 bias (1/3, 1/4 duty)
ks57c2408a/2416a microcontroller product specification september 1996 7?0 g electronics smsun g smsun segment (seg) signals the 24 lcd segment signal pins are connected to corresponding display ram locations at 1e8h?ffh. bits 0? of the display ram are synchronized with the common signal output pins com0, com1, com2, and com3. com select no-select seg t v ss v lc0 v lc0 v ss t = lcdck t figure 41. select/no-select bias signals in static display mode select no-select t v ss v ss v lc0 v lc1, 2 v lc0 v lc1, 2 com seg t t = lcdck figure 42. select/no-select bias signals in 1/2 bias display mode
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7?1 september 1996 select no-select com seg t v ss v ss v lc0 v lc1 v lc2 v lc0 v lc1 v lc2 t t = lcdck figure 43. select/no-select signals in 1/3 bias display mode
ks57c2408a/2416a microcontroller product specification september 1996 7?2 g electronics smsun g smsun
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7?3 september 1996 timing strobe bit 0 open com3 com2 com1 com0 bit 1 1 0 x x 1 1 x x 1 1 x x 1 1 x x 1 0 x x 1 0 x x 1 1 x x 0 0 x x 1 1 x x 0 1 x x 1 1 x x 1 1 x x 1 0 x x 0 1 x x 1 1 x x 0 1 x x 1 0 x x 1 1 x x 0 1 x x 0 0 x x 1 0 x x 1 1 x x 1 0 x x 0 1 x x 1e8h 1e9h 1eah 1ebh 1ech 1edh 1eeh 1efh 1f0h 1f1h 1f2h 1f3h 1f4h 1f5h 1f6h 1f7h 1f8h 1f9h 1fah 1fbh 1fch 1fdh 1feh 1ffh seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 figure 45. lcd connection example (1/2 duty, 1/2 bias)
ks57c2408a/2416a microcontroller product specification september 1996 7?4 g electronics smsun g smsun timing strobe bit 0 open com3 com2 com1 com0 bit 1 bit 2 1 1 0 x 1 0 1 x 1 1 x x 1 1 0 x 1 1 1 x 1 0 x x 1 1 0 x 1 1 1 x 1 1 x x 1 1 0 x 1 0 0 x 1 0 x x 0 1 0 x 1 1 1 x 1 1 x x 0 1 0 x 1 1 1 x 1 0 x x 1 1 0 x 0 1 0 x 1 0 x x 1 1 0 x 1 1 1 x 1e8h 1e9h 1eah 1ebh 1ech 1edh 1eeh 1efh 1f0h 1f1h 1f2h 1f3h 1f4h 1f5h 1f6h 1f7h 1f8h 1f9h 1fah 1fbh 1fch 1fdh 1feh 1ffh seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 0 0 0 figure 46. lcd connection example (1/3 duty, 1/3 bias)
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7?5 september 1996 timing strobe bit 0 com3 com2 com1 com0 bit 1 bit 2 bit 3 1 0 1 0 1 1 1 1 1 0 1 0 1 1 0 1 0 1 1 0 1 1 0 0 1 1 1 0 0 1 0 1 1 1 0 0 0 1 1 1 0 1 1 0 0 0 0 0 1 1 1 0 1 0 1 1 1 1 1 0 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 1 0 0 0 1 0 1 0 1 1 1 1 1 0 1 0 1 1 0 1e8h 1e9h 1eah 1ebh 1ech 1edh 1eeh 1efh 1f0h 1f1h 1f2h 1f3h 1f4h 1f5h 1f6h 1f7h 1f8h 1f9h 1fah 1fbh 1fch 1fdh 1feh 1ffh seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 figure 47. lcd connection example (1/4 duty, 1/3 bias)
ks57c2408a/2416a microcontroller product specification september 1996 7?6 g electronics smsun g smsun +v lcd ?v lcd 0 v seg12 v lc0 v ss seg11 v lc0 v ss com0 v lc0 v ss com0 seg11 com0 seg12 +v lcd ?v lcd 0 v t f figure 48. lcd signal waveforms in static mode
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7?7 september 1996 + v lcd ?v lcd v lc0 v ss v lc1, 2 v lc0 v ss v lc1, 2 v lc0 v ss v lc1, 2 + 1/2 v lcd ?1/2 v lcd 0 ?v lcd + 1/2 v lcd ?1/2 v lcd 0 + v lcd com1 seg9 com0 seg9 com1 seg9 com0 t f figure 49. lcd signal waveforms at 1/2 duty, 1/2 bias
ks57c2408a/2416a microcontroller product specification september 1996 7?8 g electronics smsun g smsun v lc0 v ss v lc1, 2 com0 t f v lc0 v ss v lc1, 2 com1 v lc0 v ss v lc1, 2 com2 v lc0 v ss v lc1, 2 seg12 + v lcd ?v lcd + 1/2 v lcd ?1/2 v lcd 0 com0 seg12 ?v lcd + 1/2 v lcd ?1/2 v lcd 0 + v lcd com1 seg12 ?v lcd + 1/2 v lcd ?1/2 v lcd 0 + v lcd com2 seg12 figure 50. lcd signal waveforms at 1/3 duty, 1/2 bias
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7?9 september 1996 t f + 1/3 v lcd + v lcd com2 seg12 ?1/3 v lcd 0 ?v lcd + 1/3 v lcd + v lcd com1 seg12 ?1/3 v lcd 0 ?v lcd lcd + 1/3 v lcd + v lcd com0 seg12 ?1/3 v lcd 0 ?v seg12 v v lc0 ss v lc2 v lc1 com2 v v lc0 ss v lc2 v lc1 com1 v v lc0 ss v lc2 v lc1 com0 v v lc0 ss v lc2 v lc1 figure 51. lcd signal waveforms at 1/3 duty, 1/3 bias
ks57c2408a/2416a microcontroller product specification september 1996 7?0 g electronics smsun g smsun com0 v v lc0 ss v lc2 v lc1 com1 v v lc0 ss v lc2 v lc1 com2 v v lc0 ss v lc2 v lc1 com3 v v lc0 ss v lc2 v lc1 seg20 v v lc0 ss v lc2 v lc1 com0 seg20 + 1/3 v lcd ?v lcd + v lcd ?1/3 v lcd 0 com1 seg20 + 1/3 v lcd ?v lcd + v lcd ?1/3 v lcd 0 t f figure 52. lcd signal waveforms at 1/4 duty, 1/3 bias
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7?1 september 1996 a/d converter to operate the a/d converter, one of the six analog input channels is selected by writing the appropriate value to the a/d mode register, admod. to start the converter, the adstr flag in the control register aflag must be set to "1". conversion speed is determined by the oscillator frequency and the cpu clock. when the a/d operation is complete, the eoc flag must be tested in order to verify that the conversion was successful. when the eoc value is "0", an interrupt request (intad) is issued. then, when the interrupt request has been enabled, the converted digital values stored in the data register adata can be read. "0" .2 .1 .0 admod aflag adstr eoc "0" "0" adata 8 ad5 ad4 ad3 ad2 ad1 ad0 av ref av ss resistor string digital-to-analog converter dac cmp multiplexer successive approximation logic vain intad v da 8 \ 8 data bus note : the voltage level of the avss and vss should be the same figure 53. a/d converter circuit diagram
ks57c2408a/2416a microcontroller product specification september 1996 7?2 g electronics smsun g smsun tinit one machine cycle tconv = 10 8 / fx (fx = fosc) adstr eoc intad adata previous value value remains undetermined valid data * figure 54. a/d converter timing diagram adc digital-to-analog converter (dac) the 8-bit digital-to-analog converter (dac) generates analog voltage reference values for the comparator. the dac is a 256-step resistor string type digital-to- analog converter that uses successive approximation logic to convert digital input into the reference analog voltage, v da . the v da values are input from the dac to the comparator where they are compared to the multiplexed external analog source voltage, va in . since the dac has 8-bit resolution, it generates the 256-step analog reference voltage. adc data register (adata) the a/d converter data register, adata, is an 8-bit register in which digital data values are stored as an a/d conversion operation is completed. digital values stored in adata are retained until another conversion operation is initiated. adata is addressable by 8-bit read instructions only. adc mode register (admod) the analog-to-digital converter mode register admod is used to select one of six analog channels as the analog data input source. input channels ad0?d5 (corresponding to i/o pins p9.0?9.3 and p10.0 10.1) may be used either for analog input to the a/d converter, or as normal input ports. because only one of the six ports can be selected at one time as external source of analog data, the five remaining input ports are always available for other inputs. bit 3 in the admod register is always 0. table 33. a/d converter mode register settings (1, 4-bit r/w) admod.2 admod.1 admod.0 effect of admod bit setting 0 0 0 select input channel ad0 (pin p9.0) 0 0 1 select input channel ad1 (pin p9.1) 0 1 0 select input channel ad2 (pin p9.2) 0 1 1 select input channel ad3 (pin p9.3) 1 0 0 select input channel ad4 (pin p10.0) 1 0 1 select input channel ad5 (pin p10.1)
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7?3 september 1996 adc control register (aflag) the a/d converter control register, aflag, contains the control flags used to start the a/d converter and to monitor its operational status. fdbh adstr eoc "0" "0" the adstr bit (bit 3) is the enable/disable flag for the a/d converter (adstr = a/d start). adstr is write- only and is 1-bit and 4-bit addressable. the eoc bit (end of conversion) is a flag that can be read to determine the current status of an a/d conversion operation. eoc is 1-bit or 4-bit read-only addressable. + programming tip ?configuring a/d converter input pins in this a/d converter program sample, the ad0, ad1 and ad2 pins are used as a/d input pins and the p9.3 / ad3, p10.0 / ad4, and p10.1 / ad5 pins are used as normal input pins: bitr emb bitr iead ; disable intad interrupt di ; disable all interrupts during a/d conversion ld a,#0h ld admod,a ; ad0 pin select for a/d conversion bits adstr ; a/d conversion start ad0ck btsf eoc ; a/d conversion end check jr ad0ck ; a/d conversion not completed ld ea,adata ; a/d conversion end ld ad0buf,ea ; ad0buf ? ad0 conversion data ld a,#1h ld admod,a ; ad1 pin select for a/d conversion bits adstr ; a/d conversion start ad1ck btsf eoc ; a/d conversion end check jr ad1ck ; a/d conversion not completed ld ea,adata ; ad conversion end ld ad1buf,ea ; ad1buf ? ad1 conversion data ld a,#2h ld admod,a ; ad2 pin select for a/d conversion bits adstr ; ad conversion start ad2ck btsf eoc ; ad conversion end check jr ad2ck ; ad conversion not completed ld ea,adata ; ad conversion end ld ad2buf,ea ; ad2buf ? ad2 conversion data ei ; interrupt enable bits emb btst p9.3 ; p9.3 / ad3 pin check jps aaa btst p10.0 ; p10.0 / ad4 pin check jps bbb btst p10.1 ; p10.0 / ad5 pin check jps ccc
ks57c2408a/2416a microcontroller product specification september 1996 7?4 g electronics smsun g smsun recommendation for a/d converter application the input voltage level at the ad0 - ad5 input pins must be greater than v ss and less than v dd . although v in does satisfy the absolute maximum voltage requirement, conversion data may be undefined if the v ss < v in < v dd condition is not met. to ensure the accuracy of a/d conversion data, noise entering at the a/d input pins must be eliminated. figure 49 shows the recommended circuit configuration. on the figure, values of capacitors and resistors are as follows. in addition to, r1 is variable to control the offset value. note : c1 = 10 m f, c2 = 100 to 1000 pf, c3 = 100 to 1000 pf, r1 = 50 to 100 w , r2 = 1k w . v dd v dd av ref ad0-5 av ss v ss r1 r2 c3 c1 c2 figure 55. recommendation for a/d converter
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7?5 september 1996 serial i/o interface using the serial i/o interface, you can exchange 8-bit data with an external device. the serial interface can run off an internal or an external clock source, or the tol0 signal that is generated by the 8-bit timer/counter 0, tc0. if you use the tol0 clock signal, you can modify its frequency to adjust the serial data transmission rate. internal bus lsb or msb first sbuf (8-bit) si clock selector irqs r qd clk clk clk 8 q0 q1 q2 3-bit counter clear 8 r s q so smod.7 smod.6 smod.5 smod.3 smod.2 smod.1 smod.0 sck tol0 cpu clk fxx/2 10 fxx/2 figure 56. serial i/o interface circuit diagram
ks57c2408a/2416a microcontroller product specification september 1996 7?6 g electronics smsun g smsun serial i/o mode register (smod) the serial i/o mode register (smod) specifies the operation mode of the serial interface. smod register settings enable you to select either msb-first or lsb- first serial transmission, and to operate in transmit- and-receive mode or receive-only mode. when smod.3 is set to "1", the contents of the serial interface interrupt request flag, irqs, and the 3-bit serial clock counter are cleared, and sio operations are initiated. when the sio transmission starts, smod.3 is cleared to "0". serial i/o buffer register (sbuf) when the serial interface operates in transmit-and- receive mode (smod.1 = "1"), transmit data in the sio buffer register are output to the so pin at the rate of one bit for each falling edge of the sio clock. receive data is simultaneously input from the si pin to sbuf at the rate of one bit for each rising edge of the sio clock. when receive-only mode is used, incoming data is input to the sio buffer at the rate of one bit for each rising edge of the sio clock. sbuf can be read or written using 8-bit ram control instructions. table 34. sio mode register (smod) organization smod.0 0 most significant bit (msb) is transmitted first 1 least significant bit (lsb) is transmitted first smod.1 0 receive-only mode 1 transmit-and-receive mode smod.2 0 disable the data shifter and clock counter; retain contents of irqs flag when serial transmission is halted 1 enable the data shifter and clock counter; set irqs flag to "1" when serial transmission is halted smod.3 1 clear irqs flag and 3-bit clock counter to "0"; initiate transmission and then reset this bit to logic zero smod.4 0 bit not used; value is always "0" smod.7 smod.6 smod.5 clock selection r/w status of sbuf 0 0 0 external clock at sck pin sbuf is enabled when sio operation is halted or when sck goes high. 0 0 1 use tol0 clock from tc0 0 1 x cpu clock: fxx/4, fxx/8, fxx/64 enable sbuf read/write 100 4.09 khz clock: fxx/2 10 sbuf is enabled when sio operation is halted or when sck goes high. 111 262 khz clock: fxx/2 4 notes : 1. 'fxx' = system clock; 'x' means 'don't care.' 2. khz frequency ratings assume a system clock (fxx) running at 4.19 mhz. 3. the sio clock selector circuit cannot select a fxx/2 4 clock if the cpu clock is fxx/64 .
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7?7 september 1996 sck si so irqs di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 transmit complete set smod.3 figure 57. sio timing in transmit/receive mode high impedance sck si irqs transmit complete set smod.3 di7 di6 di5 di4 di3 di2 di1 di0 so figure 58. sio timing in receive-only mode
ks57c2408a/2416a microcontroller product specification september 1996 7?8 g electronics smsun g smsun + programming tip ?setting transmit/receive modes for serial i/o 1. transmit the data value 48h through the serial i/o interface using an internal clock frequency of fx/2 4 and in msb-first mode: bits emb smb 15 ld ea,#03h ld pmg1,ea ; p0.0 / sck and p0.1 / so ? output ld ea,#48h ; ld sbuf,ea ; ld ea,#0eeh ld smod,ea ; sio data transfer ks57c2408 external device sck / p0.0 so / p0.1 2. use cpu clock to transfer and receive serial data at high speed: bitr emb ld ea,#03h ld pmg1,ea ; p0.0 / sck and p0.1 / so ? output, p0.2 / si ? input ld ea,tdata ; tdata address = bank0(20h?fh) ld sbuf,ea ld ea,#4fh ld smod,ea ; sio start bitr ies ; sio interrupt enable stest btstz irqs jr stest ld ea,sbuf ld rdata,ea ; rdata address = bank0 (20h?fh)
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7?9 september 1996 + programming tip ?setting transmit/receive modes for serial i/o (continued) 3. transmit and receive an internal clock frequency of 4.09 khz (at 4.19 mhz) in lsb-first mode: bitr emb ld ea,#03h ld pmg1,ea ; p0.0 / sck and p0.1 / so ? output, p0.2 / si ? input ld ea,tdata ; tdata address = bank0 (20h?fh) ld sbuf,ea ld ea,#8fh ld smod,ea ; sio start ei bits ies ; sio interrupt enable ints push sb ; store smb, srb push ea ; store ea bitr emb ld ea,tdata ; ea ? transmit data ; tdata address = bank0 (20h?fh) xch ea,sbuf ; transmit data ? receive data ld rdata,ea ; rdata address = bank0 (20h?fh) bits smod.3 ; sio start pop ea pop sb iret ks57c2408 external device sck / p0.0 so / p0.1 si / p0.2
ks57c2408a/2416a microcontroller product specification september 1996 7?0 g electronics smsun g smsun + programming tip ?setting transmit/receive modes for serial i/o (concluded) 4. transmit and receive an external clock in lsb-first mode: bitr emb ld ea,#02h ld pmg1,ea ; p0.1/ so ? output, p0.0/ sck and p0.2/ si ? input ld ea,tdata ; tdata address = bank0 (20h?fh) ld sbuf,ea ld ea,#0fh ld smod,ea ; sio start ei bits ies ; sio interrupt enable ints push sb ; store smb, srb push ea ; store ea bitr emb ld ea,tdata ; ea ? transmit data ; tdata address = bank0 (20h?fh) xch ea,sbuf ; transmit data ? receive data ld rdata,ea ; rdata address = bank0 (20h?fh) bits smod.3 ; sio start pop ea pop sb iret external device sck / p0.0 so / p0.1 si / p0.2 ks57c2408
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7?1 september 1996 electrical data table 35. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating units supply voltage v dd ?0.3 to + 7.0 v input voltage v i1 applies to i/o ports 4 and 5 only. pull-up resistors are individually assignable to pins at ports 4 and 5, or they can remain open-drain. ?0.3 to v dd + 0.3 (with pull-up resistor) ?0.3 to + 9.0 (open-drain) v v i2 all i/o ports except 4 and 5 0.3 to v dd + 0.3 output voltage v o ?0.3 to v dd + 0.3 v output current high i oh one i/o port active ?15 ma all i/o ports active ?30 output current low i ol one i/o port active + 30 (peak value) ma + 15 * total value for ports 0, 2, 3, and 5 + 100 (peak value) + 60 * total value for ports 4, 6, and 7 + 100 operating temperature t a ?40 to + 85 c storage temperature t stg ?65 to + 150 c * the values for output current low ( i ol ) are calculated as peak value ? ``` duty . table 36. d.c. electrical characteristics (t a = ?40 c to + 85 c, v dd = 2.7 v to 6.0 v) parameter symbol conditions min typ max units input high voltage v ih1 all input pins except those speci- fied below for v ih2 ? ih4 0.7 v dd ? dd v v ih2 ports 0?, 6, 7, 9, 10, and reset 0.8 v dd v dd v ih3 ports 4 and 5 with pull-up resistors assigned 0.7 v dd v dd ports 4 and 5 open-drain 0.7 v dd 9 v ih4 x in , x out , and xt in v dd ?0.5 v dd input low voltage v il1 ports 3, 4, 5 0.3 v dd v v il2 ports 0?, 6, 7, 9, 10, and reset 0.2 v dd v il3 x in , x out , and xt in 0.4
ks57c2408a/2416a microcontroller product specification september 1996 7?2 g electronics smsun g smsun table 36. d.c. electrical characteristics (continued) (t a = ?40 c to + 85 c, v dd = 2.7 v to 6.0 v) parameter symbol conditions min typ max units output high voltage v oh1 v dd = 4.5 v to 6.0 v i oh = ?1 ma ports 0, 2, 3, 6, 7, and bias v dd ?1.0 v i oh = ?100 m av dd ?0.5 v oh2 v dd = 4.5 v to 6.0 v i oh = ?100 m a; port 8 only v dd ?2.0 i oh = ?30 m av dd ?1.0 output low voltage v ol1 v dd = 4.5 v to 6.0 v i ol = 15 ma ports 4 and 5 only 0.4 2 v i ol = 1.6 ma ports 0, 2, 3, 6, and 7 only 0.4 i ol = 400 m a ports 0, 2, 3, 6, and 7 only 0.2 v ol2 v dd = 4.5 v to 6.0 v i ol = 100 m a; port 8 only 1 i ol = 50 m a1 input high leakage current i lih1 v in = v dd all input pins except ports 4 and 5, x in , x out , and xt in 3 m a i lih2 v in = v dd x in , x out , xt in only 20 i lih3 v in = 9 v ports 4 and 5 are open-drain 20 input low leakage current i lil1 v in = 0 v all input pins except x in , x out , xt in and reset ?3 m a i lil2 v in = 0 v x in , x out , xt in ,only ?20 output high leakage current i loh1 v out = v dd all output pins except for port 4 and port 5 3 m a i loh2 ports 4 and 5 are open-drain v out = 9 v 20 output low leakage current i lol v out = 0 v 3 m a
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7?3 september 1996 table 36. d.c. electrical characteristics (concluded) (t a = ?40 c to + 85 c, v dd = 2.7 v to 6.0 v) parameter symbol conditions min typ max units pull-up resistor r l1 v in = 0 v; v dd = 5 v 10% port 0, 1 (not p1.3), 2, 3, 6, and 7 15 40 80 k w v dd = 3 v 10% 30 200 r l2 v out = v dd ?2 v v dd = 5 v 10% ports 4 and 5 only 15 40 70 v dd = 3 v 10% 10 60 r l3 v in = 0 v v dd = 5 v 10% reset 100 230 400 v dd = 3 v 10% 200 490 800 lcd voltage dividing resistor r lcd 50 100 140 k w com output impedance r com v dd = 5 v 10% 3 6 k w v dd = 3 v 10% 10 15 seg output impedance r seg v dd = 5 v 10% 3 20 k w v dd = 3 v 10% 10 60
ks57c2408a/2416a microcontroller product specification september 1996 7?4 g electronics smsun g smsun table 36. d.c. electrical characteristics (concluded) (t a = ?40 c to + 85 c, v dd = 2.7 v to 6.0 v) parameter symbol conditions min typ max units supply current (1) i dd1 (2) v dd = 5 v 10% (3) 4.19 mhz crystal oscillator c1 = c2 = 22 pf 2.5 8 ma v dd = 3 v 10% (4) 0.62 1.2 i dd2 (2) idle mode; v dd = 5 v 10% 4.19 mhz crystal oscillator c1 = c2 = 22 pf 0.6 1.8 v dd = 3 v 10% 0.25 1.0 i dd3 (5) v dd = 3 v 10% 32 khz crystal oscillator 30 90 m a i dd4 (5) idle mode; v dd = 3 v 10% 32 khz crystal oscillator 515 i dd5 stop mode; xt in = 0 v v dd = 5 v 10% 0.5 5 v dd = 3 v 10% 0.1 3 notes : 1. currents in the following circuits are not included; on-chip pull-up resistors, internal lcd voltage dividing resistors, output port drive currents and a/d converter. 2. data includes power consumption for subsystem clock oscillation. 3. for high-speed controller operation, the power control register (pcon) must be set to 0011b. 4. for low-speed controller operation, the power control register (pcon) must be set to 0000b. 5. when the system clock control register, scmod, is set to 1001b, main system clock oscillation stops and the subsystem clock is used.
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7?5 september 1996 table 37. a.c. electrical characteristics (t a = ?40 c to + 85 c, v dd = 2.7 v to 6.0 v) parameter symbol conditions min typ max units instruction cycle time (1) t cy v dd = 4.5 v to 6.0 v 0.95 64 m s v dd = 2.7 v to 4.5 v 3.8 64 with subsystem clock (fxt) 114 122 125 tcl0, tcl1 input frequency f ti0 , f ti1 v dd = 4.5 v to 6.0 v 0 1 mhz v dd = 2.7 v to 4.5 v 275 khz tcl0, tcl1 input high, low width t tih0 , t til0 t tih1 , t til1 v dd = 4.5 v to 6.0 v 0.48 m s v dd = 2.7 v to 4.5 v 1.8 sck cycle time t kcy v dd = 4.5 v to 6.0 v external sck source 800 ns internal sck source 950 v dd = 2.7 v to 4.5 v external sck source 3200 internal sck source 3800 sck high, low width t kh , t kl v dd = 4.5 v to 6.0 v external sck source 400 ns internal sck source t kcy /2 50 v dd = 2.7 v to 4.5 v external sck source 1600 internal sck source t kcy / 2 150 si setup time to sck high t sik external sck source 100 ns internal sck source 150 si hold time to sck high t ksi external sck source 400 ns internal sck source 400 output delay for sck to so t kso v dd = 4.5 v to 6.0 v external sck source 300 ns internal sck source 250 v dd = 2.7 v to 4.5 v external sck source 1000 internal sck source 1000
ks57c2408a/2416a microcontroller product specification september 1996 7?6 g electronics smsun g smsun table 37. a.c. electrical characteristics (continued) (t a = ?40 c to + 85 c, v dd = 2.7 v to 6.0 v) parameter symbol conditions min typ max units interrupt input high, low width t inth , t intl int0 (2) m s int1, int2, int4, ks0?s7 10 reset input low width t rsl input 10 m s notes : 1. unless otherwise specified, instruction cycle time condition values assume a main system clock ( fx ) source. 2. minimum value for int0 is based on a clock of 2t cy or 128/fx as assigned by the imod0 register setting. measurement points 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd figure 59. a.c. timing measurement points (except for x in and xt in ) cpu clock = 1/n x oscillator frequency (n = 4, 8, 64) 1 2 3 4 5 6 7 supply voltage (v) 250 khz 500 khz 750 khz 1.00 mhz 1.0475 mhz 15.6 khz cpu clock figure 60. standard operating voltage range
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7?7 september 1996 table 38. input/output capacitance (t a = 25 c, v dd = 0 v ) parameter symbol condition min typ max units input capacitance c in f = 1 mhz; unmeasured pins are returned to v ss 15 pf output capacitance c out 15 pf i/o capacitance c io 15 pf table 39. a/d converter electrical characteristics (t a = ?10 c to + 70 c, v dd = 3.5 v to 6.0 v, v ss = av ss = 0 v) parameter symbol condition min typ max units resolution 8 8 8 bit absolute accuracy (1) 2.5 v < av ref < v dd 1.5 lsb conversion time (2) t con 100/fx (3) m s analog input voltage v ian ?v ss ?v ref v analog input impedance r an 1000 m w notes : 1. absolute accuracy does not include the quantization error ( 1/2 lsb). 2. conversion time is the time required from the moment a conversion operation starts until it ends (eoc = 0). 3. 'fx' is the abbreviation for main system clock.
ks57c2408a/2416a microcontroller product specification september 1996 7?8 g electronics smsun g smsun table 40. main system clock oscillator frequencies (t a = ?40 c + 85 c, v dd = 2.7 v to 6.0 v) oscillator type clock conditions min typ max unit ceramic fx 0.4 4.5 mhz crystal fx 0.4 4.19 4.5 mhz resistor-capacitor (rc) fx v dd = 5 v 0.4 2 mhz external clock x in input 0.4 4.5 mhz note : 'fx' is the main system clock. table 41. main system clock oscillation stabilization times (t a = ?40 c + 85 c, v dd = 2.7 v to 6.0 v) oscillator type conditions min typ max unit ceramic stabilization occurs when v dd is equal to the minimum oscillator voltage range. 4ms crystal v dd = 4.5 v to 6.0 v 10 ms v dd = 2.7 v to 4.5 v 30 ms external clock x in input high and low level width (t xh , t xl ) 100 ns note : oscillation stabilization time is the time required for the main system clock to return to normal oscillation frequency after a power-on occurs, or when stop mode is terminated. table 42. subsystem clock oscillator frequencies (t a = ?40 c + 85 c, v dd = 2.7 v to 6.0 v) oscillator type clock conditions min typ max unit crystal fxt 32 32.768 35 khz external clock xt in input (fxt) 32 100 khz note : 'fxt' is the subsystem clock table 43. subsystem clock oscillation stabilization time (t a = ?40 c + 85 c, v dd = 2.7 v to 6.0 v) oscillator type conditions min typ max unit crystal v dd = 4.5 v to 6.0 v 1.0 2 s v dd = 2.7 v to 4.5 v 10 s external clock xt in input high and low level width (t xth , t xtl ) 515 m s note : oscillation stabilization time is the time required for the subsystem clock to return to normal oscillation frequency after a power-on occurs.
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7?9 september 1996 table 44. ram data retention supply voltage in stop mode (t a = ?40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr normal operation 2.0 7.0 v data retention supply current i dddr v dddr = 2.0 v 0.1 10 m a release signal set time t srel normal operation 0 m s oscillator stabilization wait time (note1) t wait released by reset ? 17 / fx ms released by interrupt (note 2) ?s notes : 1. during oscillator stabilization wait time, all cpu operations must be stopped to avoid instability during oscillator start-up. 2. use the basic timer mode register (bmod) interval timer to delay execution of cpu instructions during the wait time. t srel t wait v dd reset execution of stop instruction v dddr data retention mode stop mode internal reset operation idle mode operating mode figure 61. stop mode release timing when initiated by reset v dd execution of stop instruction v dddr data retention mode stop mode t wait t srel idle mode normal operating mode power-down mode terminating signal (interrupt request) figure 62. stop mode release timing when initiated by interrupt request
ks57c2408a/2416a microcontroller product specification september 1996 7?0 g electronics smsun g smsun xin t xl t xh 1 / fx v dd ?0.5 v 0.4 v figure 63. clock timing measurement at x in xtin t xtl t xth 1 / fxt v dd ?0.5 v 0.4 v figure 64. clock timing measurement at xt in tcl t til t tih 1 / f ti 0.8 v dd 0.2 v dd figure 65. tcl timing reset t rsl 0.2 v dd figure 66. input timing for reset signal
product specification ks57c2408a/2416a microcontroller g electronics smsun g smsun 7?1 september 1996 int0, 1, 2, 4 ks0 to ks7 t intl t inth 0.8 v dd 0.2 v dd figure 67. input timing for external interrupts and quasi-interrupts sck t kl t kh t cky 0.8 v dd input data output data 0.2 v dd 0.8 v dd 0.2 v dd si so t sik t ksi t kso figure 68. serial data transfer timing
ks57c2408a/2416a microcontroller product specification september 1996 7?2 g electronics smsun g smsun notes

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